Transcript Field Programmable Gate Arrays

Introduction to Field
Programmable Gate Arrays
(FPGAs)
EDL Spring 2016
Johns Hopkins University
Electrical and Computer Engineering
March 2, 2016
What are FPGAs?
• Field Programmable Gate Array
• Integrated circuit that can be
configured by the user to emulate
any digital circuit as long as there are
enough resources
• Array of configurable logic blocks
(CLBs) connected through
programmable interconnects (switch
boxes)
Time line of Programmable Devices
1945 1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000
Transistors
ICs (General)
SRAMs & DRAMs
Microprocessors
SPLDs
CPLDs
ASICs
FPGAs
FPGA vs. ASIC (Application-Specific IC)
FPGA Market
FPGA Specifications
• Block RAM (~1,000-20,000 Kb)
• Clock speed (~100-600Mhz)
• I/O (100s of I/O ports)
• USB 2.0/3.0
• Ethernet
• PCI-Express
• Resources (Configurable Logic Blocks)
• DSP Slices
• VCCIO supplies
Why Use FPGAs?
• Reprogrammable!
• High-Level/Behaviors Hardware Description Language!
• Logic/Timing Simulation!
• Parallel, Real-time Processing!
• Relatively small-size and light-weight!
• Interface with PC other devices/systems (i.e. Camera)!
• Prototyping before designing custom chip!
Field Programmable Gate Arrays FPGA
• Field Programmable Gate Array
• ‘Simple’ Programmable Logic Blocks
• Massive Fabric of Programmable Interconnects
• Standard CMOS Integrated Circuit fabrication process as
for SRAM memory chips (Moore’s Law)
Huge Density of Logic Block ‘Islands’
1,000 … 100,000’s
in a ‘Sea’ of Interconnects
FPGA Architecture
Field Programmable Gate Arrays FPGA
Logic Blocks
• Logic Functions implemented in Look Up Table LUTs.
• Flip-Flops. Registers. Clocked Storage elements.
• Multiplexers (select 1 of N inputs)
16-bit SR
16x1 RAM
a
b
c
d
4-input
LUT
y
mux
flip-flop
q
e
clock
clock enable
set/reset
FPGA Fabric
Logic Block
Look Up Tables LUTs
•
LUT contains Memory Cells to implement small logic functions
•
Each cell holds ‘0’ or ‘1’ .
•
Programmed with outputs of Truth Table
•
Inputs select content of one of the cells as output
•
Configured by re-programmable SRAM memory cells
3 Inputs LUT -> 8 Memory Cells
16-bit SR
16x1 RAM
3 – 6 Inputs
a
b
c
d
4-input
LUT
y
mux
flip-flop
q
e
clock
clock enable
set/reset
SRAM
SRAM
Multiplexer MUX
Static Random Access Memory
SRAM cells
Logic Blocks
• Larger Logic Functions built up by connecting many
Logic Blocks together
Logic Blocks
• Larger Logic Functions built up by connecting many
Logic Blocks together
• Determined by SRAM cells
SRAM
SRAM cells
Clocked Logic
• Registers on outputs. CLOCKED storage elements.
• Synchronous FPGA Logic Design, Pipelined Logic.
• FPGA Fabric Pulse from Global Clock (e.g. LHC BX
frequency)
16-bit SR
16x1 RAM
a
b
c
d
e
4-input
LUT
y
mux
flip-flop
q
clock
clock enable
set/reset
FPGA Fabric
Special Routing for Clocks
Clock from Outside world (eg LHC bunch frequency)
Input Output I/O Getting data in and out
1
0
2
7
General-purpose I/O
Up to
> 1,000
I/O “pins”
(several 100 MHz)
banks
0 through
7
3
6
4
5
Input Output I/O Getting data in and out
1
0
2
7
General-purpose I/O
Up to
> 1,000
I/O “pins”
(several 100 MHz)
banks
0 through
7
3
6
4
Special I/O SERIALISERS
~ 10 Gbps transfer rates
5
Transceiver block
Differential pairs
FPGA
Optical TRx
Designing Logic with FPGAs
• Design Capture.
• High level Description of Logic Design.
• Graphical descriptions
• Hardware Description Language (Textual)
Textual HDL
Graphical State Diagram
When clock rises
If (s == 0)
then y = (a & b) | c;
else y = c & !(d ^ e);
Top-level
block-level
schematic
Graphical Flowchart
Block-level schematic
Hardware Description Languages
•
•
•
•
Language describing hardware (Engineers call it FIRMWARE)
Doesn’t behave like “normal” programming language ‘C/C++’
Describe Logic as collection of Processes operating in Parallel
Language Constructs for Synchronous Logic
• Compiler (Synthesis) Tools recognise certain code constructs
and generates appropriate logic
• Not all constructs can be implemented in FPGA!
• 2 Popular languages are VHDL , VERILOG
• Easy to start learning… Hard to master!
VHDL
ENTITY Declaration Input Output to Module (STD LOGIC)
SIGNALS Declaration WIRES
CONCURRENT ASSIGNMENTS
CONDITIONAL ASSIGNMENTS => MULTIPLEXERS
VHDL
PROCESS Declaration. CONCURRENT functions. Synchronous Logic.
COMPONENT Declaration
Designing Logic with FPGAs
•
High level Description of Logic Design
•
Hardware Description Language (Textual)
•
Compile (Synthesis) into NETLIST.
•
Boolean Logic Gates.
•
Target FPGA Device
•
•
•
Schematic
capture
Gate-level
netlist
BEGIN CIRCUIT=TEST
INPUT SET_A, SET-B,
DATA, CLOCK,
CLEAR_A, CLEAR_B;
OUTPUT Q, N_Q;
WIRE
SET, N_DATA, CLEAR;
Mapping
Routing
GATE G1=NAND (IN1=SET_A,
IN2=SET_B,
OUT1=SET);
GATE G2=NOT (IN1=DATA,
OUT1=N_DATA);
GATE G3=OR
(IN1=CLEAR_A,
IN2=CLEAR_B,
OUT1=CLEAR);
GATE G4=DFF (IN1=SET, IN2=N_DATA,
IN3=CLOCK, IN4=CLEAR,
OUT1=Q, OUT2=N_Q);
END CIRCUIT=TEST;
Mapping
Bit File for FPGA
Packing
Design Flow
Place-andRoute
•
Logic Simulation
Fully-routed physical
(CLB-level) netlist
Timing analysis
and timing report
Gate-level netlist
for simulation
SDF (timing info)
for simulation
Designing Logic with FPGAs
•
High level Description of Logic Design
•
Hardware Description Language (Textual)
•
Compile (Synthesis) into NETLIST.
•
Boolean Logic Gates.
•
Target FPGA Device
•
•
•
Schematic
capture
Gate-level
netlist
BEGIN CIRCUIT=TEST
INPUT SET_A, SET-B,
DATA, CLOCK,
CLEAR_A, CLEAR_B;
OUTPUT Q, N_Q;
WIRE
SET, N_DATA, CLEAR;
Mapping
Routing
GATE G1=NAND (IN1=SET_A,
IN2=SET_B,
OUT1=SET);
GATE G2=NOT (IN1=DATA,
OUT1=N_DATA);
GATE G3=OR
(IN1=CLEAR_A,
IN2=CLEAR_B,
OUT1=CLEAR);
GATE G4=DFF (IN1=SET, IN2=N_DATA,
IN3=CLOCK, IN4=CLEAR,
OUT1=Q, OUT2=N_Q);
END CIRCUIT=TEST;
Mapping
Bit File for FPGA
Packing
Design Flow
Place-andRoute
•
Logic Simulation
Fully-routed physical
(CLB-level) netlist
Timing analysis
and timing report
Gate-level netlist
for simulation
SDF (timing info)
for simulation
Designing Logic with FPGAs
•
High level Description of Logic Design
•
Hardware Description Language (Textual)
•
Compile (Synthesis) into NETLIST.
•
Boolean Logic Gates.
•
Target FPGA Device
•
•
•
Schematic
capture
Gate-level
netlist
BEGIN CIRCUIT=TEST
INPUT SET_A, SET-B,
DATA, CLOCK,
CLEAR_A, CLEAR_B;
OUTPUT Q, N_Q;
WIRE
SET, N_DATA, CLEAR;
Mapping
Routing
GATE G1=NAND (IN1=SET_A,
IN2=SET_B,
OUT1=SET);
GATE G2=NOT (IN1=DATA,
OUT1=N_DATA);
GATE G3=OR
(IN1=CLEAR_A,
IN2=CLEAR_B,
OUT1=CLEAR);
GATE G4=DFF (IN1=SET, IN2=N_DATA,
IN3=CLOCK, IN4=CLEAR,
OUT1=Q, OUT2=N_Q);
END CIRCUIT=TEST;
Mapping
Bit File for FPGA
Packing
Design Flow
Place-andRoute
•
Logic Simulation
Fully-routed physical
(CLB-level) netlist
Timing analysis
and timing report
Gate-level netlist
for simulation
SDF (timing info)
for simulation
Configuring an FPGA
• Millions of SRAM cells holding LUTs and Interconnect Routing
• Volatile Memory. Lose configuration when board power is
turned off.
• Keep Bit Pattern describing the SRAM cells in non-Volatile
Memory e.g. PROM or Digital Camera card
JTAG Port
• Configuration takes ~ secs
Configuration data in
Configuration data out
= I/O pin/pad
Programming
Bit File
= SRAM cell
SRAM
JTAG Testing
Field Programmable Gate Arrays FPGA
• Large Complex Functions
• Re-Programmability, Flexibility.
• Massively Parallel Architecture
• Processing many channels simultaneously cf MicroProcessor
•
•
•
•
Fast Turnaround Designs 
Standard IC Manufacturing Processes. Moore’s Law 
Mass produced. Inexpensive. 
Many variants. Sizes. Features. 
• Power Hungry 
• No Analogue 
FPGA Trends
• State of Art is 40nm on 300 mm wafers
• Top of range >500,000 Logic Blocks
• >1,000 pins (Fine Pitched BGA)
1.00E+09
1.00E+08
Number of LCs
1.00E+07
1.00E+06
1.00E+05
1.00E+04
1.00E+03
1.00E+02
1985
• Logic Block cost ~ 1$ in 1990
• Today < 0.1 cent
1990
1995
2000
2005
2010
2015
2020
2025
Year
1
• Problems
• Power
• Leakage currents
$ / LC
0.1
0.01
0.001
0.0001
1990
1995
2000
2005
2010
2015
Sequential vs. Combinational Logic
Sequential Circuits
Combinational Logic (Larger circuits difficult to predict)
 Synchronous Logic driven by a CLOCK
 Registers, Flip Flops (Memory)

Inputs
Sequential Circuits
Combinational Logic (Larger circuits difficult to predict)
 Synchronous Logic driven by a CLOCK
 Registers, Flip Flops (Memory)

Intermediate
New Output every clock edge
Inputs
CLOCK
EDGES
Register
Sequential Circuits
Combinational Logic (Larger circuits difficult to predict)
 Synchronous Logic driven by a CLOCK
 Registers, Flip Flops (Memory)

Intermediate
New Output every clock edge
Inputs
Clock Rate determines speed
CLOCK
EDGES
Register
Comb Logic Must meet Timing
=> Predictable circuits
Shift Registers,
Pipelines,
Finite State Machines
…
FPGA Example 1: Two Wheel Balancing Robot
FPGA Example 2: Face Detection
References
• The Design Warrior’s Guide to FPGAs
• Clive Maxfield, Newnes Elsevier
• VHDL for Logic Synthesis
• Andrew Rushden, Wiley
• FPGA manufacturer web sites
• www.xilinx.com
• www.altera.com
• FPGA Online
• www.pldesignline.com
• www.fpgajournal.com
• www.doulos.com