Transcript component

Overview
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von Neumann Architecture
Computer component
Computer function
Instruction set
CPU
Memory
I/O
von Neumann architecture
All contemporary computer design are
base on three key concepts :
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Data and instructions are stored in a single
read-write memory.
The contents of this memory are addressable
by location
Execution occurs in a sequential fashion from
one instruction to the next
Computer Component
Arithmetic and Logical Unit (ALU)
 Central Processing Unit (CPU)
 Control Unit (CU)
 Memory Unit
 I/O devices
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Storage devices
System bus
Computer Function
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The basic function is program
execution.
The Program to be executed consists of
a set of instruction stored in memory.
The CPU does actual work by executing
instructions specified in the program.
Instruction Sets
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Instruction : An individual pattern which
instructs the computer to do a task.
Consists of two part
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OP-code
Operand or Address
Instruction set classifies CPU into model
or family
Computer Component
Central Processing Unit (CPU)
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Processor
Where the data are manipulated by
executing instruction
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Two basic parts are
Control Unit (CU)
 Arithmetic and Logical Unit (ALU)
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Executing Instruction
Instruction cycle
 Fetch cycle : CPU read (fetches)
instructions from memory one at a
time.
 Execution cycle : CPU executes each
instruction
Instruction Cycle
Start
Are the Instruction awaiting execution?
Yes
Fetch the next instruction
Execute the instruction
No
Are there interrupts require services?
Yes
Transfer control to interrupt handling program
No
halt
CPU
Control Unit (CU)
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Controls each part of components to
perform instruction or program
procedure
load program into memory
 fetch instruction one at a time
 decode, create and send control signals
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CPU
Control Unit Components
The CU has three components
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Program Counter(PC): contains the address
of the next instruction to be executed
Instruction Register (IR) : holds the actual
instruction that is being executed
Instruction Decoder : determines the type of
operation currently in the IR and sends
control signal to implement that operation
Control Unit Function
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Instruction sequencing : selects
instruction from memory to executed
Instruction Interpretation : interprets
and sends control signals to CPU
through control lines
Instruction sequencing
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0
PC = PC’ + K
PC : next instruction address
PC’: previous instruction address
k : instruction length
34
15
Op Code
Address
(a) Instruction Format
0001 = Load AC From Memory
0010 = Store AC To Memory
0101 = Add to AC from Memory
(b) Partial List of Opcodes
Example of program execution
300
301
302
940
941
300
301
302
940
941
300
301
302
940
941
1940
5941
2941
..
0003
0002
1940
5941
2941
..
0003
0002
..
1940
5941
2941
0003
0002
300
PC
AC
IR
300
301
302
.. CPU Registers
1940
1
..
301
0003
5941
300
301
302
PC
AC
IR
3
..
302
0005
2941
940
941
940
941
300
301
302
PC
AC
IR
5
940
941
1940
5941
2941
..
0003
0002
..
..
1940
5941
2941
0003
0002
1940
5941
2941
0003
0005
..
300
0003
1940
PC
AC
IR
2
..
..
301
0005
5941
PC
AC
IR
316 + 216 = 516
302
0005
2941
4
PC
AC
IR
6
Instruction Interpretation
C’’ in
Control Unit
C’ in
Input data
C’ out
ALU
Implementation Method
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C” out
Hardwired Control Unit
Microprogram Control Unit
Output data
CPU
Arithmetic and Logical Unit (ALU)
The ALU has two part
 Functional unit : perform the operation
(arithmetic operations and logical
operations)
 Register : hold operands, results, errors
and status information
CPU
Functional Unit
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Arithmetic
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integer adder
integer subtractor
integer multiplier
integer divider
arithmetic shift unit
incrementor &
decrementor
floating-point
arithmetic unit
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Logical
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comparator
logic shift unit
NOT unit
AND unit
OR unit
CPU
Operation of functional unit
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Arithmetic
+ add
- subtract
* multiply
/ divide
^ raise by a power
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Logical
=, = equal, not equal
>, > greater than,
not greater than
<, < less than,
not less than
>, > greater than or
equal, not ...
<, < less than or equal,
not ...
CPU
Diagram of functional unit
Start/Stop signal
from control unit
Left X
Z Result
Z := X op
op Y
Right Y
E Error/Status
Timing signal
?
Register
Control signal
Data
CPU
Register
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high-speed memory location
contain data for functional unit
register size -> word size
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16-bit processor
32-bit processor
64-bit processor
CPU
Register Type
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Accumulator register : operand, result
General purpose register
Index register : address
Special-purpose register
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Overflow register
Carry register
Shift register
Temporary register
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Stack register
Floating-point register
Status information
register
CPU
Register & Memory
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reference by name instead of unsigned
binary address : A, R1
higher speed than memory
use for specific job, not general job
use specific path for transfer data
Processor families
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Intel : Pentium
AMD : K6, K7
Cyrix : Cyrix
Motorola : 680X0
Computer Component
Memory
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Stores and retrieves (fetch) information
It is divided into cells, and data are accessed
by means of the unique address of the cell.
2n words of m-bit memory with addresses
0,1,2,…,2n-1
Access data in memory
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Store
นำข้อมูลเข้ำไปบรรจุใน memory ณ ตำแหน่งที่รบบุ
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Fetch
ดึงข้อมูลจำก memory
Memory component
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Memory Address Register(MAR): contains the
address of the word we want to store or fetch
Memory Buffer Register (MBR) : contains the
contents of the location we want to do with
Decoder : decodes address to be the location
Read/Write Control Lines : provides the signal
to control the memory perform a fetch or
store operation.
Memory component
address
0000
0001
0002
0003
0004
size …
…
…
…
…
…
2n-1
m-1 .. .. .. ... 2 1 0
Memory width
Decoder
MAR
Read control lines
Write control lines
MBR
Flow of information
Control Signal
Read procedure
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Stores address of data in MAR.
Sends read signal through read control line.
Decodes data in MAR to be the location in
memory bank.
Reads data from that location and stores in
MBR.
Write procedure
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Stores address of data in MAR.
Stores data we want to write in MBR.
Sends write signal throgh write control line.
Decodes data in MAR to be the location in
memory bank.
Writes data in MBR into that location.
Memory Hierarchy
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Register
Caches : L1, L2, ..
Main Memory
Magnetic Disk
Magnetic Tape
Characteristics
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Location
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CPU
Internal
External
Capacity
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Word size
Number of words
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Unit of Transfer
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Word
Block
Access Method
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Sequential
Direct
Random
Associative
Characteristics (cont.)
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Performance
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Access time
Memory cycle time
Transfer rate
Physical type
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Semiconductor
Magnetic surface
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Physical
characteristics
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Volatile/Non-volatile
Erasable/Non-erasable
RAM
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Random Access Memory
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EDO RAM (Extended Data-Out RAM)
DRAM (Dynamic RAM)
SRAM (Static RAM)
SDRAM (Synchronous DRAM)
DDR SDRAM (Double Data Rate SDRAM)
VRAM (Video RAM)
ROM
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Read only memory : contain a
permanent pattern of data for starting a
computer to work
ROM Typed
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PROM (Programmable ROM)
EPROM (Erasable ROM)
EEPROM (Electrical Erasable PROM)
Data in ROM
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Important memory routines of system
Loader program
Compiler and interpreter
Important error-recovers procedures
some part of Operating System
Cache Memory
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Disk cache
Memory cache
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L1 cache : internal cache
L2 cache : external cache
Word transfer
L1
CPU
L2 Cache
Block transfer
Main
Memory
Input/Output
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I/O module
I/O function
I/O devices components
Data transfer Techniques
I/O Module
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The entity with in a computer responsible for the
control of one or more external devices and for the
exchange of data between those devices and main
memory and/or CPU register.
The major function for an I/O module
 control and timing
 CPU communication
 Device communication
 Data buffering
 Error detection
I/O Function
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The third key element of a computer is a set
of I/O module.
Each module interface to the system bus or
central switch and controls one or more
peripheral devices.
I/O module contains logic for performing a
communication function between the
peripheral and the bus.
The Component of I/O devices
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I/O Mechanism
The mechanical, electrical that make up
I/O devices
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I/O Controller
The component that manages the flow of
information between the I/O device and the
computer
Data Transfer Techniques
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Programmed I/O
Interrupt Driven I/O
DMA I/O Controller
Programmed I/O
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Data are exchanged between the CPU and the
I/O module.
The CPU executes a program that gives it
direct control of the I/O operation.
When the CPU issues to the I/O modules, it
must wait until the I/O operation is complete.
If the CPU is faster than the I/O module, this is
wasteful of CPU time.
Issue read command
to I/O module
CPU --> I/O
Read status
of I/O module
I/O --> CPU
Not
Ready
No
Check status
Error Condition
Ready
Read word from
I/O module
I/O --> CPU
Write word into
memory
CPU --> Memory
Done?
Yes
Programmed I/O
Interrupt-Driven I/O
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The CPU send START signal to I/O controller
for start working.
After send signal, the CPU can continue their
jobs
When I/O controller finish work, it send
interrupt signal to the CPU
The CPU suspend their works and load data
into memory
Issue read command
to I/O module
Read status
of I/O module
Check status
No
CPU --> I/O
Do Something Else
Interrupt
I/O --> CPU
Error Condition
Ready
Read word from
I/O module
I/O --> CPU
Write word into
memory
CPU --> Memory
Done?
Yes
Interrupt-Driven I/O
DMA I/O Controller
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Consist of 2 registers
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DAR (DMA Address Register) : stores
address of data in memory
WC (Word Count Register) : specifies data
size to write in memory
DMA I/O Controller (cont.)
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Store address of data in DAR
Store size of data in WC
Send START signal to I/O Controller
When finishing data transfer, it send interrupt
signal to the CPU
Issue read block
command
to DMA module
CPU --> DMA
Read status
of DMA module
Interrupt
DMA --> CPU
Do Something Else
Direct Memory Access