Transcript EECT 7327 - Data Converters

Data Converters
EECT 7327
Comparator
CMOS Comparator
–1–
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Comparator
Vo
“1”
Vth
Vi
Vth
Vi
“0”
Vo (“Digital”)
Φ
Transfer characteristic
(ideal)
Circuit symbol
Detects the polarity of the analog input signal and produces a digital output
(1 or 0) accordingly – threshold-crossing detector
–2–
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Applications
• Voltage/current level comparison (A/D conversion)
• Digital communication receivers (“slicer” or decision circuit)
• Sense amplifier in memory readout circuits
• Power electronics with digital control (dc-dc converter)
–3–
Data Converters
EECT 7327
Comparator
Design Considerations
• Accuracy (offset, noise, resolution)
• Settling time (tracking BW, regeneration speed)
• Sensitivity (gain)
• Metastability (any decision is better than no decision!)
• Overdrive recovery (memory)
• CMRR
• Power consumption
–4–
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Comparator
Vm
Vi
Vth

Vo
Vth
Amplification

Vth
Clipping
•
Precise gain and linearity are often unnecessary → simple, low-gain, openloop, wideband amplifiers + latch (positive feedback)
•
More gain can be derived by cascading multiple gain stages
•
Built-in sampling function with latched comparators
–5–
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Multi-Stage Preamp
…
Vi
A(ω)
A(ω)
Vi
…
CL
Vo
A(ω)
A ω 
Vi+1
gmVi
RL
CL
gmVi+1
…
ω0  1/ RLCL



A0
A0

AN  ω   


 1 ω / ω 2
1

j

ω
/
ω
0 


0

N
N stages:
A N  ω  ω3dB 
1
A 0N
N

, ω3dB  ω0 2  1
2
–6–
A0
1  j  ω / ω0
N




Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Step Response
V1
Vin
gmVin
RL
V1  Vin  A 0 1 e  t/ τ 
V2
CL
gmV1
 Vin  A 0  t / τ  for t  τ
…
 Vin  gmRL 
 Vin 
t
RLCL
gm
t
CL
Ignore RL in all stages,
2
t
t
gm
1
1
1  gm 
2
V1 
g
V
dt

V

t,
V

g
V
dt


 Vin  t
m in
in
2
m 1


CL 0
CL
CL 0
2  CL 
N
t
1
tN  gm 
For small VN, VN 
gm VN1dt  
 Vin

CL 0
N!  CL 
–7–
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Optimum N
10
2
V /V =10
o i
Vo/Vi=100
V /V =1000
For small Vo ,
i
N
t N  gm 
 Vi
Vo  
N!  CL 
L
m
t/(C /g )
o
10
1
C
t L
gm
10
  Vo  
N!   
  Vi  
1
N
0
1
2
3
4
5
6
7
8
9
10
N
•
Given A0 = Vo/Vi, Nopt can be determined with the above equation
•
For A0 < 100, typical N value ranges between 2 and 4
–8–
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Comparison
10
C
t L
gm
6
  Vo  
N!   
  Vi  
1
N
L
m
t/(C /g )
8
4
latch : t 
N=1
N=3
N=5
Latch
2
0
0
10
10
1
V /V
o
10
2
10
CL  Vo 
ln  
gm  Vi 
3
i
•
A higher A0 (= Vo/Vi) requires a larger N
•
In comparison, latches regenerate faster than preamps
–9–
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Multi-Stage PA Offset
Vos1
Vos2
Vos3
Individual stage
A1
A2
A3

Vos
Total input-referred
A1
A2
A3
A T  A1  A 2  A 3
Vos  Vos1 
Vos2
V
 os3
A1 A1  A 2
– 10 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Input Offset Cancellation
Φ2'
Φ1
C
Vos
Vi
Vo
Φ2
A
•
AC coupling at input with input-referred offset stored in C
•
Two-phase operation, one phase (Φ2) is used to store offset
– 11 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Offset Storage – Φ2
Φ2'
Vc
Vc   A Vc  Vos 
Vos
Vo
Φ2
A

A
 Vos
1 A
 Vos

Closed-loop stability (amplifier in unity-gain feedback)
Ref: J. L. McCreary and P. R. Gray, “All-MOS charge redistribution analog-to-digital
conversion techniques. I,” JSSC, vol. 10, pp. 371-379, issue 6, 1975.
– 12 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Amplifying Phase – Φ1
Φ1
Vc
Vos
Vi
Vo
A

Vo   A Vin  Vc  Vos 
V 

  A  Vin  os 
1 A 

Input - referred offset :
Vos
Vos,in 
1 A
•
Offset cancellation is incomplete if A is finite
•
Input AC coupling attenuates signal gain
– 13 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
CF and CI of Switches
Φ2'
Vc
Vos
Φ1
Vo
Φ2
A
Φ2'
Φ2
•
What’s the optimum phase relationship between Φ2 and Φ2'?
•
Bottom-plate sampling → Φ2' switches off slightly before Φ2 (note the
operation in this phase is signal independent anyway)
– 14 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Output Offset Cancellation
Φ1
Vos
C
Vi
Φ1
Vo
Φ2
A
Φ2'
•
AC coupling at output with offset stored in C
•
A must be small and well controlled (independent of Vo)
•
Does not work for high-gain op-amps
– 15 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Offset Storage – Φ2
Vos
Φ2
Vc
A
Φ2'

Vc  A Vos   AVos
•
Closed-loop stability is not required
•
CF and CI of Φ2' gets divided by A when referred to input
Ref: R. Poujois and J. Borel, “A low drift fully integrated MOSFET operational
amplifier,” JSSC, vol. 13, pp. 499-503, issue 4, 1978.
– 16 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Amplifying Phase – Φ1
Φ1
Vos
Vc
Vi
Φ1
Vo
A
Vo  A Vi  Vos   AVos
 AVin

Input - referred offset :
Vos,in = 0
•
Cancellation is complete if A is constant (independent of Vo)
•
AC coupling at output attenuates signal gain
– 17 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Offset Cancellation w/ Auxiliary Input
Vo+
C1
+
Vi
Vi-
S1
S2
S3
S4
RL
Vos1
Gm1
Vos2
Gm2
RL
S5
S6
C2
Vo-
•
Gm1 and Gm2 are the preamp and latch, respectively
•
A form of output offset cancellation technique
Ref: B. Razavi and B. A. Wooley, “Design techniques for high-speed, high-resolution
comparators,” JSSC, vol. 27, pp. 1916-1926, issue 12, 1992.
– 18 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Offset Sampling
Vo+
C1
+
Vi
Vi-
S1
S2
S3
S4
RL
Vos1
Gm1
Vos2
Gm2
RL
S5
S6
• S3-S6 closed
• S1-S2 open
C2
Vo-
•
Gm1 and Gm2 are grounded and the PFB of Gm2 is disabled
•
Vos1 and Vos2 are amplified by Gm1 and Gm2 to appear at Vo
•
When S5 & S6 open (slightly before S3 & S4), offset voltage is sampled
and stored in C1 and C2
•
CF/CI of S5 & S6 gets divided by (Gm1/Gm2) when referred to input
– 19 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Comparison
Vo+
C1
+
Vi
Vi-
S1
S2
S3
S4
RL
Vos1
Gm1
Vos2
Gm2
RL
S5
S6
• S3-S6 open
• S1-S2 closed
C2
Vo-
•
Differential input is amplified by Gm1 to establish an imbalance at the
output and AC coupled to the input of Gm2
•
Gm2 starts regeneration with this imbalance
– 20 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Potential Problems
Vo+
C1
+
Vi
Vi-
S1
S2
S3
S4
RL
Vos1
Gm1
Vos2
Gm2
RL
S5
S6
C2
Vo-
•
Very complicated → slow conversion speed
•
C1 and C2 and their parasitics add loading to the output
•
Finite on-resistance of S5 & S6 cannot completely break PFB
•
CF/CI imbalance of S5 & S6 can trigger regeneration
– 21 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Razavi’s Comparator
Vo+
C1
+
Vi
Vi-
S1
S2
S7
S3
RL
S9
S5
S4
RL
Gm2 S
10
S6
Gm1
C2
Vo-
Even more complicated!
– 22 –
S8
Data Converters
EECT 7327
Comparator
Overdrive Recovery
– 23 –
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Overdrive Recovery Test
Φ
Φ
Vi
Vi = VFS
Vi
Vi = -LSB/2
Vo+
Vi = LSB/2
Vo+
Vo
Vo
“0”
Vo
Vi = VFS
-
“1”
Vo
Case I
-
Case II
A small input (±0.5 LSB) is applied to the comparator input in a cycle right
after a full-scale input is applied; the comparator should be able to resolve
to the right output in either case → memoryless
– 24 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Passive Clamp
M3
Vo +
M4
Vo-
M5
•
Limit the output swing
with diode clamps →
signal-dependent Ro
•
Clamps add parasitics
to the PA output
M6
Vi+
M1
M2
Vi-
– 25 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Active Reset
M3
Φ
M4
Vo +
Vo-
•
Kill PA gain with a
crowbar switch →
time-dependent Ro
•
Switch adds parasitics
to the PA output
M5
Vi+
M1
M2
Vi-
– 26 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
PA Autozeroing
M3
Φ2'
Φ1
C
Vo+
Vo-
Φ2'
Vos
Vi
Vo
Φ2
M4
Vi+
A
M5
M6
M1
M2
•
Two-phase operation, Φ2 phase is used for offset storage
•
Autozeroing switch Φ2' also resets and removes the PA memory
– 27 –
Vi-
Data Converters
EECT 7327
Comparator
CMOS Preamplifier
– 28 –
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Pull-Up
 NMOS diode pull  up :
AV  
Pull-up
Vo+
Vi+
VoM1
M2
gm1

gmL
W L 1
W LL
 PMOS diode pull  up :
Vi-
AV  
gm1
μ W L 1
 n
gmL
μp W L L
 Resistor pull  up :
A V  gm1  RL
•
NMOS pull-up suffers from body effect, affecting gain accuracy
•
PMOS pull-up is free from body effect, but subject to P/N mismatch
•
Gain accuracy is the worst for resistive pull-up as resistors (poly, diffusion,
well, etc.) don’t track transistors; but it is fast!
– 29 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
To Obtain More Gain
M3
Ip
Ip
M4
Vo +
Vi+
VoM1
Vi-
M2
• Higher gain w/o CMFB
• Needs biasing for Ip
• M3 & M4 may cut off for
large Vin, resulting in a
slow recovery
I
AV  
• Ip diverts current away
from PMOS diodes (M3
& M4), reducing (W/L)3
gm1
μ  I 2  W L 1
 n 
gm3
μp  I 2  Ip  W L 3
– 30 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Bult’s Preamp
M3 M5
M6 M4
Vo +
Vi+
VoM1
Vi-
M2
• NMOS diff. pair loaded
with PMOS diodes and
PMOS latch (PFB)
• High DM gain, low CM
gain, good CMRR
• Simple, no CMFB
• (W/L)34 > (W/L)56
needs to be ensured
for stability
M7
Ref: K. Bult and A. Buchwald, “An embedded 240-mW 10-b 50-MS/s CMOS ADC in
1-mm2,” JSSC, vol. 32, pp. 1887-1895, issue 12, 1997.
– 31 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
DM
M3 M5
M6 M4
Vo +
Vi+

VoM1
M2
1
gm3
-1
gm5
ro3
ViVid
gm1Vid
ro1
M7
DM gain : A V
dm
ro5
 1
 gm1  
 gm3

 1 
g r
 //ro1//ro3 //ro5    m1 o1
//  
3
 gm5 

– 32 –
Vod
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
CM
M3 M5
M6 M4
Vo +
Vi+
VoM1
M2
1
gm3

Vgs1
Vi-
1
gm5
gm1Vgs1
Vic
2ro7
M7
CM gain : A V cm  
Voc
 1
gm1
1 
1

//



1 2gm1ro7  gm3 gm5 
2  gm3  gm5  ro7
– 33 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Song’s Preamp
M3
M4
RL
• NMOS diff. pair loaded
with PMOS diodes and
resistors
RL
Vo+
VoX
Vi+
M1
M2
Vi-
• High DM gain, low CM
gain, good CMRR
• Simple, no CMFB
• Gain not well-defined
M5
Ref: B.-S. Song et al., “A 1 V 6 b 50 MHz current-interpolating CMOS ADC,” in
Symp. VLSI Circuits, 1999, pp. 79-80.
– 34 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Song’s Preamp
1
gm3
ro3
RL
Vgs1
gm1Vid
Vid
ro1
gm1Vgs1
Vic
Vod
Voc
2ro5
DM
AV
dm
CM
 gm1  ro1//ro3 //R L 
A V cm  
 gm1RL

– 35 –
gm1
1

1 2gm1ro5 gm3
1
2gm3ro5
Data Converters
EECT 7327
Comparator
CMOS Latch
– 36 –
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Static Latch
• Active pull-up and pulldown → full CMOS
logic levels
Vi+
M3
M4
M2
M1
Vi-
Φ
Q+
Q-
M7
M5
M6
• Very fast!
• Q+ and Q- are not well
defined in reset mode
(Φ = 1)
• Large short-circuit
current in reset mode
• Zero DC current after
full regeneration
• Very noisy
– 37 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Semi-Dynamic Latch
Φ
Vi+
M8
M3
M4
M2
M1
Vi-
Φ
Q+
Q-
M7
M5
• Diode divider disabled
in reset mode → less
short-circuit current
• Pull-up not as fast
• Q+ and Q- are still not
well defined in reset
mode (Φ = 1)
• Zero DC current after
full regeneration
M6
• Still very noisy
– 38 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Current-Steering Latch
Φ
RL
Vi+
M1
Φ
RL
M2
Q+
Q-
M7
Vi-
M3
M4
Φ
M5
M6
• Constant current
→ very quite
• Higher gain in
tracking mode
• Cannot produce
full logic levels
• Fast
• Trip point of the
inverters
M8
– 39 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Dynamic Latch
Φ
M7
M5
M6
Q+
M1
M9
M3
• Full logic level after
regeneration
Φ
M10
M4
M2
• Zero DC current in
reset mode
• Q+ and Q- are both
reset to “0”
QΦ
Vi+
Φ
M8
Vi-
• Slow
• No seed voltage
Ref: A. Yukawa, “A CMOS 8-Bit High-Speed A/D Converter IC,” JSSC, vol. 20, pp.
775-779, issue 3, 1985.
– 40 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Modified Dynamic Latch
Φ
M7
M5
M6
Φ
M8
+
-
Q
Q
Φ
M9
M3
Vi+
• Slow
M4
M1
M2
• Q+ and Q- are both
reset to “0”
• Full logic level after
regeneration
Φ
M10
• Zero DC current in
reset mode
Vi-
• No seed voltage
Ref: T. B. Cho and P. R. Gray, “A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,”
JSSC, vol. 30, pp. 166-172, issue 3, 1995.
– 41 –
Data Converters
EECT 7327
Comparator
Professor Y. Chiu
Fall 2014
Cho’s Comparator
Φ
M7
M5
M6
Q+
QM9
Φ
M10
M3
W
W

G1  k   i  Vi   Vt   R  VR   Vt  
L
L

W
W

G2  k   i  Vi   Vt   R  VR   Vt  
L
L


Φ
Vi+
Φ
M8
M4
M1 M1R
M2R M2
VR-
Vi-
Vth =
WR
  VR   VR  
Wi
VR+
M1R and M2R added to set the comparator threshold
– 42 –