Transcript E f

Lecture7
Active matrix displays
Active matrix – transistor(s) in each pixel
 Needed in all high resolution displays: LCD, OLED, epaper etc
 Control voltage (LCD) or current (OLED)
 Transistors on glass – thin film transistors (TFT)
 Not the same as transistors on Si : FET and BJT
 Low temperature processing below glass softening
 Review of microelectronics technology: principles
and processing

Semiconductors



Insulator : NaCl, LiF …
Semiconductor (Group IV, III-V, II-VI) : GaAs, InP,
ZnSe, Si, Ge …
Metal : Na, Ag, …
Ec
Ev
Bandgap




Bandgap is related to the ionicity of the molecular
bond. LiF is very ionic and has large bandgap. ZnSe
is not so ionic and has a smaller bandgap. Si-Si is
covalent and has even smaller bandgap
Wide bandgap semiconductor and insulators are
getting indistinguishable: ZnO, GaN,…
Molecular solid – different from inorganic solid in
terms of bonding – hydrogen bond
Important feature of semiconductor – conductivity
s has strong temperature dependence
Bandgaps of TFT materals
Si
Ge
1.11 eV
0.67 eV
GaAs
CdSe
SiC
GaN
1.43 eV
1.73 eV
2.86 eV
3.2 eV
ZnO
TiO2
CeO2
3.3 eV
3.4 eV
3.2 eV
InSnO
ZrO2
Y 2 O3
3.5-4.06 eV
5-7 eV
5.6 eV
Intrinsic carrier density


Density of state :
N ( E )  8 M c
Probability a state is occupied :
f(E ) 

Thus electron density :

n

Ec
N ( E ) f ( E ) dE 
2 me 3
h3
1
E  Ef 
1  exp 

 kT 
2
 E  Ec 
Nc F  f


 kT


where

Same for holes, thus :

The intrinsic electron concentration :
 2 me kT 
Nc  2 

2
 h

E  Ec
3 /2
Mc
 Eg 

np  N c Nv exp  

kT


 Eg
ni  N c Nv exp  
 2 kT




Doped semiconductor
N-type : n = Nd , p = ni2 / Nd
 P-type : p = Na , n = ni2 / Na
 Donors : group 5 elements (P, As)
 Acceptors : group 3 elements (Ga, In)
 Doping : thermal diffusion, ion implantation
 Thermal diffusion : predeposition, drive-in diffusion
 Dopant profile:

z
 2 Dt

C z , t   C s erfc 



Position of the Fermi level


EF is inside the
energy gap for
most situations
EF can be inside
the conduction or
valence band for
degenerate
doping
Conductivity
Drift velocity :
v=mE
 Current density :
J = nqv = nqm E
 Conductivity :
s = nqm
 With both electrons and holes :
s = nqme  pqmh
 Mobility :
m  qt / m*

me (cm2/V-s) mh (cm2/V-s)
Crystalline Si
1350
480
Polycrystalline Si
10-500
10-300
Microcrystalline Si
1-10
1-10
Amorphous Si
1
0.01
Silicon bandgap and absorption



Silicon is the most
important
semiconductor
because we can
form very good
oxide on it to form
the gate insulator
Silicon wafer is
opaque
How about thin film?
• 1 mm thick Si film has
~36% transmission
• Appears reddish since
blue is absorbed
p-n junction


Fermi level is constant if there is no current
Build-in potential
p
Vbuilt in 
n
kT  N a N d
ln
 n 2
q
 i




Current

Drift of majority carrier – drift current

Diffusion of minority carrier – diffusion current
D 
mkT
q
J n z   qmn n z E z   qDn
dn z 
dz
J p z   qmp p z E z   qD p
dp z 
dz
Dn (cm2/s)
Dp (cm2/s)
a-Si
0.025
0.0025
Poly-Si
12.5
7.5
Current across junction
In n-region, current is drift of n
 Near the junction, it is diffusion of p to the n-region
 Voltage drop is mostly across junction – small drift
current

Itotal
In
Ip
 qD p pn qDn n p

 Lp
Ln

J 

 qV / kT
e
1



L  Dt
Field effect transistor (FET)

Depletion mode and enhancement mode
Source
n
Gate
Drain
Pinch-off - just
like JFET
n
p+
p+
n+



p
n+
Enhancement
like MOSFET
TFT is enhancement mode only
NMOS – electrons – channel lightly p-doped
PMOS – holes – channel lightly n-doped
Thin film transistors
MOSFET is on crystalline silicon
 TFT – active channel can be just a thin film – no bulk
effect – same formulas
 Thin film can be amorphous (a-Si) or polycrystalline
(p-Si) or single crystalline (SOI, SOS). SOI TFT quality is
similar to MOSFET
 TFT technology – most important is active layer
 Dominant material is a-Si – 90% of TFT market
 p-Si has 10% and increasing (i-phone is p-Si)
 Other materials: CdSe, Ge, SiGe, ZnO, InZnO,
organic materials
G

S
D
Energy band diagram in N-type TFT
Note : Band diagram is for
energy of electrons. Thus
positive voltage means negative
electron energy in band diagram
EC
0V
EF
EV
Holes
MOS
9V
Energy band diagram in P-type TFT
MOS
－9V
0V
EC
EF
EV
MOS capacitor
Flat band voltage
Vfb = -fms
Inversion
For flat band,
Vth = Vox + Ec –Ef
Thus in general
Vth = Vox + Ec –Ef + Vfb
(not quite accurate as we
shall see)
Crux: voltage drop across
the gate oxide
Gate material

Polycrystalline silicon as gate
has the advantages of
• Compatible with high
temperature processing
• Close match between Fm and
Fs. Thus very small flat band
voltage
• Need p+ poly for NMOS and n+
poly for PMOS

Metal gate has the
advantages of
• Simple deposition process
• Low T processing
Gate dielectric material



Silicon oxide and nitride and sometimes oxynitride
Sometimes Al2O3 or HfO2 or Ta2O5 or other kinds of
oxides for high k (larger gate capacitance for lower
threshold)
Thermally grown for uniformity
Inversion criteria – surface potential
VG = Vfb + V = Vfb + Vox + Vs
Surface charges
Depth of charged area
does not increase upon
stronger reverse bias.
The charge density on
the surface increases.
Threshold voltage

The threshold voltage is the gate voltage needed to induce an
inversion layer
Vth = Vfb + Vox + Vs

Thus
If Na = 1016, the fF ~ 0.35V and Vs is about 0.7V
 Voltage across the gate oxide is simply

Vox 
Qs
Q
 sd
C ox
g

At onset of inversion, we can still assume that the charge is due to
depletion

Thus
Threshold voltage optimization





To reduce Vth, need high k dielectric and thin gate oxide layer
Vth can also be tuned by channel doping, i.e. changing Na
We need to include body effect for FET on bulk silicon. Similar
to double gate TFT with back gate grounded. For TFT on glass,
there is no body effect
If there are trapped surface charges, Vfb will change and the
threshold voltage will shift
This is a serious problem for TFT
MOSFET I-V curve


Channel created by
gate voltage
(enhancement mode)
Linear region:
I D  mC g

W
1


VD VG Vth  VD 
L
2


Saturation region:
I D  mC g
W
VD VG Vth 2
2L
m is field effect mobility – not
exactly the same as Hall
mobility. Field mobility is
strongly influenced by
qualify of the gate interface
Electrical characteristics

Transconductance
(gain) in the linear
region
G 
 Id

I d
W
 mC g Vd
V g
L
vs Vg is called
transfer curve
Id vs Vd is called
output curve
On resistance

In the linear region, the conductance in the output
curve is
Gd 

The channel resistance is 1/G
R

I d
W
 mC g VG Vth 
Vd
L
1
L

G d mC gW VG Vth 
Also the transconductance is
G 
I d
W
 mC g VG Vth 
V g
L
I-V curve (transfer characteristics)
LTPS TFT : p-Type
1.00E-03
120
1.00E-05
Vds=-0.1V
1.00E-06
2
源漏电流 （A）
场效应迁移率 （cm /Vs）
140
Vds=-5V
1.00E-04
100
1.00E-07
80
1.00E-08
GM
1.00E-09
60
W/L=30微米/10微米
Tox＝50纳米
1.00E-10
40
1.00E-11
20
1.00E-12
-15
0
-13
-11
-9
-7
-5
栅电压（V）
-3
-1
1
3
Output curves for n-Type TFT
1.4
Vg＝5V
1.2
线性区 Vg－Vt>Vds
源漏电流 （A）
1
Vg＝4V
饱和区 Vds>Vg－Vt
0.8
0.6
Vg＝3V
0.4
截止区 V g<V t
0.2
0
0
1
2
3
4
5
6
7
8
9
10
源漏电压 （V）
Switching TFTs (pixel) : work in cut-off region and linear region
 Driver TFTs: work in saturation region

Output curves for p-Type TFT
8.00E-01
Vg＝－5V
7.00E-01
源漏电流 （A）
6.00E-01
5.00E-01
Vg＝－4V
4.00E-01
3.00E-01
2.00E-01
Vg＝－3V
1.00E-01
0.00E+00
-10
-9
-8
-7
-6
-5
源漏电压 （V）
-4
-3
-2
-1
0
Criteria for good TFT




On-off ratio: should be >106 (109 for Si MOSFET)
Threshold voltage: operating gate voltage should be < 5V
Subthreshold slope (S): inverse slope of log(Ids) vs Vgs
It can be shown that
kT
S 
q






1  C d 

C g 

Where Cd is the depletion layer capacitance and Cg is the
gate capacitance. Should also depend on grain structure
Dilemma: reducing Vth will reduce Cg and increase S
S should be as small as possible, <0.3 V/dec for making
circuits. MOSFET is < 0.07 V/dec. The previous curve for a-Si
gives 1 V/dec – marginal
Oxide TFT has best S (0.1V/dec), LTPS: 0.1 – 0.8V/dec
depending on quality
Field effect mobility


Different from Hall effect mobility
Field effect mobility is obtained from I-V curves – more
meaningful for studying LTPS and a-Si
Key parameter in device fabrication
1.00E-04
0
d
Ld
m
G
W0Vd
Cg 
1.00E-05
200
1.00E-06
（A）
I
W
G  d  mC g V d
V g
L

Vd

1.00E-07
源漏电流
W 
1
I d  mC g
V

V

Vd
 g
th
L 
2
( Vd  V g  Vth )
250
1.00E-08
150
GM
100
1.00E-09
W/L=30微米/10微米
Tox＝50纳米
1.00E-10
Vds＝0.1V
50
1.00E-11
1.00E-12
0
-3
-2
-1
0
1
2
3
4
5
6
7
栅电压 （V）
8
9
10
11
12
13
14
15
场效应迁移率（cm2/Vs）

Hall mobility





Hall mobility is a property of the bulk material
Hall effect: Hall voltage balances the Lorentz force
Field effect mobility reflects the quality of the interface since
all the charges are confined in the interface inversion layer
FM is generally smaller than HM
Best Si FM is 600 cm2/V-s while HM is 1350 cm2/V-s for crystalline
Si. LTPS FM is <500 cm2/V-s
Response times
mV
v drift 
L
L2
t 

v drift
mV
L
Need short gate channel and high mobility for fast response
a-Si
p-Si
c-Si
Mobility
1 cm2/ V-s
50-600 cm2/ V-s
1200 cm2/ V-s
Design rule
5mm
1mm
0.1mm
Max clock rate
0.5 MHz
100-500 MHz
1000 GHz
Processing
temperature
550oC
620oC
1200oC
*SVGA display at 60Hz requires 30MHz
Amorphous silicon growth





Obtained by CVD thin film growth at T < 600C
CVD is better than PVD in general
SiH4 → Si + 4H
No crystal structure (long range order). But there is short range
order – coordination; needs H2 passivation
Band tailing – fuzzy gap
Polycrystalline Si




Needed for high resolution display and for OLED
Formed by thin film growth at 600C < T < 1000C
LPCVD or PECVD
SiH4 → Si + 4H
Can obtain p-Si by annealing of a-Si as well
• Solid phase crystallization (SPC), excimer laser annealing
(ELA), metal induced crystallization (MIC)

Band structure and spectrum same as c-Si unless
grains are very small (<1 mm)
a
b
MILC Front
c
C
d
MILC/MILC
Collision
Boundary
HTPS and LTPS

HTPS – annealing at high T, use quartz substrates
•
•
•
•

High quality TFT possible
Used in LCD light valves for projectors
Major supplier – SONY and Seiko-Epson
Process like silicon wafer – fully integrated drivers
LTPS – annealing at T < 620C
• Used in high resolution small displays where integrated
drivers are important (low interconnect counts)
• Excimer laser annealing (ELA) : standard technology
• Variation of ELA – SLS
• MIC – still research stage
a-Si vs p-Si
a-Si TFT
p-Si TFT
Mobility
<1 cm2/Vs
10-600 cm2/Vs
Circuits on glass
No
Yes
Aperture ratio
Small
Large, saves energy
Stability
Poor in presence of
current
Stable at all times
Masks
5, not self aligned
4 with fancy dual
level mask
4 standard, self
aligned
Cost
Low
High with ELA
Low with MIC
Active matrix driving of LCD



One active element for every pixel to hold the voltage
Voltage is held constant by the TFT with a pulse (gate + data)
input
Diodes or TFT (diode seems easy but abandoned)
Aperture ratio = area of ITO electrode /
area of pixel
Diode addressing


Easy fabrication – but not high quality, large leakage
The two diodes should have different threshold
voltages
xi
yj
Vpixel
Double diode layout


Disadvantage – large leakage as compared to TFT
Limited voltage range
ITO scan line
Al data line
TFT addressing
Gate
Source
Vpixel
ITO scan line
Al data line
p-Si TFT structures
Self-aligned
a-Si TFT structure
Same as p-Si except there is no self aligned process
 Metal source/drain always
 Only NMOS possible
 For both a-Si and p-Si, metal gate is used. No p-Si
gate as in MOSFET since high temperature step is
not possible
 For p-Si both NMOS and PMOS possible depending
on implantation of source/drain. Thus CMOS circuits
possible

Voltage inversion
Voltage inversion can be either frame inversion or
column inversion or pixel inversion. But in all cases,
decay is asymmetrical. This leads to flickering. Thus no
decay is preferred. Need large VHR.
Vcom
Voltage holding ratio (VHR)

Voltage decays exponentially between gate
pulses
V t   Vo exp t / t 

Define VHR

Thus
V ( t ) rms
VHR 
Vo
VHR 
t
2Tf
1  e
 2T f / t

Voltage holding ratio (VHR)



Usually need VHR > 99% or DV/V = 0.01
Small VHR will give flicker effect (human eye is very sensitive
to small light level changes)
Thus t > 0.8 s for 60Hz frame rate
t/Tf
VHR
1
0.75
2
0.80
3
0.85
4
0.89
5
0.91
10
0.95
20
0.975
50
0.99
Voltage decay factors





Voltage decays by RC decay of LC cell + leakage current of
TFT
RC time = r  1013 Wcm x 5 o  4.4 s. No problem here
Thus voltage decay is due mostly to TFT leakage
I off T f  C px DV
V C
This is equivalent to t of t  o px
I off
Total decay time
I
1
1

 off
t RC px Vo C px



e.g. If Ioff = 3x10-12 amp, V = 5V, t = 0.8s, then Cpx > 1 pF
Capacitance of LC cell is only ~ 0.2-0.3 pF
Need to fabricate separately Cpx
Pixel capacitor





LC between electrodes forms a capacitor
Usually not enough to hold the voltage
Need a pixel cap to hold the voltage
Pixel cap is usually formed between ITO and scan line of the
next row
Cap insulator = gate oxide
A
C px 
d
Using above example, if we need
1pF capacitor, if gate oxide =
100nm thick, then cap area
should be 5x10-9 m2 or
50mmx100mm
•Note : This capacitor will reduce
the useful aperture ratio
ITO scan line
Al data line
Aperture ratio








AR = useful light transmission area / pixel area
AR is limited by (1) TFT area and data scan lines, (2)
pixel capacitor
For 17” SXGA, subpixel = 125 mm x 375 mm
TFT = 100 mm x 10 mm
ITO line has to be wide in order to make pixel cap
(50 mm x 100 mm)
Black matrix is needed to cover non electrode area
AR ~ 70-80% for TV
AR < 50% for small panel and high ppi
Current on-off ratio requirement

Charging: need to have voltage across LC in a
short time, say 1/5 of Tf. Thus Q = Ion x Tf/5 = Cp x Vsel
I on  5 C pxV sel
N
Tf
DV
I off  C px
Tf

Leakage

Thus on-off ratio required

For SXGA and 99% VHR
V
I on / I off  5 N sel
DV
I on
 5  10 5
I off

Typical on-off ratio of a-Si TFT is 106
New idea : use LCD as e-book








If the voltage can be held for a long time, then we can
decrease the frame rate and use the LCD as e-book
This will require the RC time to be long and the leakage on the
TFT to be very small
Example: frame rate of 100 sec
r  200s, r > 4x1014 W-cm. This should be possible with some
improvement. Currently r ~1014 W-cm
DV
I off  C px
Tf
implies that
But Ion to be large enough to charge the pixel in a short time,
not the Tf/5 as before, but probably Tf/200
Ion
 2  10 7
Thus for SXGA and 99% VHR, on-off ratio should be
Ioff
This is possible with good TFT. The biggest limit to ultra-low
frame rate is the RC decay of the LC cell
LTPS
LTPS is needed to increase aperture ratio for high
resolution LCD
 Rule of thumb: LTPS is needed for >150 dpi
 LTPS is also needed for OLED as current is too small
with a-Si
 LTPS is needed for system-on-panel
 Dominant technology is ELA and SLS

Metal induced crystallization
Ni or Al
 Annealing at 650C
 NiSi formation
 NiSi nodule migration towards a-Si region
 Decomposed NiSi  p-Si
 Many variations: MIC, MILC, MIUC, CGS, GGS, DGS,
TIGR
 Lateral, unilateral, continuous grain, giant grain,
defined grain, transistor in grain

Nickel Distribution
a-Si
MILC
104
Intensity (Counts/Second)
High Ni concentration
at the MILC Front
~0.4 at% Ni
103
~0.02 at% Ni
102
101
MILC Front
(a-Si)
10
(MILC)
(MIC)
0
0
Scanning SIMS Profiling
MIC/MILC Interface
10
20
30
Scan Distance (mm)
40
Performance of MIC poly-Si TFT
N-channel
P-channel
MIUC
MILC
MIUC
MILC
78
70
98
75
3.0
3.8
-4.2
-5.7
1.1
1.4
1.0
1.5
Ioff (pA/mm)
(|Vd| = 5V)
1.8
17
0.8
470
Ion/Ioff
(|Vd| = 5V)
1.4x107
9.3x105
3.4x107
3.6x104
mFE (cm2/Vs)
Vth (V)
(|Vd| = 5V)
S
(V/decade)
Comparison of LTPS poly-Si TFT performance
Comparison of different crystallization Methods

ELA:
• High performance poly-Si TFT
• Meet the requirements from system-on-panel display devices
• High capital and running cost
• Critical processing condition, thus low yield

MIC/MILC/MIUC:
• Low-cost, high yield, high-performance poly-Si
• Large grain size, good uniformity in large area
• Under developing, not mature enough for manufacturing
• High leakage current due to residual Nickel and grain
boundary defects

DPSS、SLS/….:
• Super large grain, device quality almost as high as c-Si MOS
• Low productivity
Development Trend of System-on-Panel (SOP)
Display Based on LTPS poly-Si TFT
C-Si Driver &
Controller
DC
Clock source
Data Generator
Scan Driver
Driver
LTPS Display Panel
Using the high quality LTPS-TFT based CMOS technology to implement the
integration of scanning driver, data driver, as well as more complex circuits
which have some functions of display controller, with the active matrix on
the same glass substrate.
 Not only decreasing the pin number of the display panel, but also
squeezing the market share of c-Si based peripheral IC chips(?)
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Development Trend of System-on-Panel (SOP)
Display Based on LTPS poly-Si TFT
Based on high quality LTPS-TFT
PMOS, developing simple
fabrication process flow, the
number of the photo masks is
the same as to or less than that
for making a-Si TFT active
matrix panel.
 Providing more cost benefits to
compete with a-Si TFT active
matrix display.
 HKUST developed PMOS LTPSTFT active matrix :
• Using poly-Si to prepare
electrodes
• SOP AMLCD: 4 masks
• SOP AMOLED: 5 masks
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LTPS SOP Panel and LTPS
Large area active matrix display
a-Si TFT active matrix display
New materials
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Oxide semiconductor: ZnO and IGZO
Very high mobility and very easy to make
Sputtering, no need for expensive PECVD
Doping by O or H, no need for expensive ion implantation
Reliability issue has been solved
Practical device soon
Newer materials: graphene, sputtered III-V semiconductor