Transcript Lecture 01

ECE 546
Introduction
Spring 2014
Jose E. Schutt-Aine
Electrical & Computer Engineering
University of Illinois
[email protected]
ECE 546 – Jose Schutt-Aine
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Future System Needs and Functions
Digital Wireless
Auto
MEMS
Analog, RF
Computer
Consumer
2.5
Limits of Optical
Log (Capacity Gb/s)
2
1.5
1
0.5
0
1980
1985
1990
1995
2000
2005
2010
A
High bandwidth
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High-speed Digital
2
Demand in the Information Age
Information-oriented living
* Shopping / events / traffics
* Pastime / learning / sightseeing
* Administrative services for residents
Required media and
the amount of information
100 Mbps per home
Source: ITRCS
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PCI
• PC Interface
For external cards
Graphics, Network, Sound, etc…
Parallel
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PCI-Express
• Computer Expansion Card Standard
Replaced older PCI
Based on serial links
Capacity up to 1 Gb/s
V3.0 scheduled for 2010
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Universal Serial Bus (USB)
• Interfaces devices to computers
No rebooting
Low power
No need for external power supply
480 Mb/s
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IDE
• Expansion Card Standard
Replaced older PCI
Based on serial links
Capacity up to 1 Gb/s
V3.0 scheduled for 2010
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Serial - ATA
• Storage interface
Replaces older parallel ATA or IDE
Based on serial links
Capacity up to 3 Gb/s
Hot swapping capability
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Computer Interconnections
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Motherboards and Backplanes
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10
Cables and Transmission Lines
twisted pairs
coaxial
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Cable Specifications
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Semiconductor Technology Trends
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Signal Delay Trend
Signal Delay
gates delay
interconnect delay
Delay for Metal 1 and Global Wiring versus Feature Size
Global
Wiring w/o
Repeaters
Global
Wiring w
Repeaters
Local
Wiring
Gate
Delay
Source: ITRS roadmap 2004
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The Interconnect Bottleneck
Al
3.0 mW -cm
Cu
1.7 mW -cm
SiO2
k = 4.0
Low k
k = 2.0
Al & Cu .8m Thick
Al & Cu Line 43m Long
SPEED/PERFORMANCE ISSUE
45
40
Gate Delay
35
Sum of Delays, Cu & Low K
30
Delay (ps)
Gate wi Al & SiO2
Sum of Delays, Al & SiO2
Interconnect Delay, Al & SiO2
25
Interconnect Delay, Cu & Low K
20
15
10
Gate
5
0
650
595
540
485
430
375
320
265
210
155
100
Generation (nm)
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MOS Technology Trends
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Interconnect
• Total interconnect length (m/cm2) – active wiring
only, excluding global levels will increases:
Year
Total
Length
2003
2004
2005
2006
2007
2008
2009
579
688
907 1002 1117 1401 1559
• Interconnect power dissipation is more than 50% of
the total dynamic power consumption in 130nm and
will become dominant in future technology nodes
• Interconnect centric design flows have been adopted
to reduce the length of the critical signal path
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5-Layer Interconnect Technology 0.25 mm
Vertical parallel-plate capacitance
Vertical parallel-plate capacitance (min width)
Vertical fringing capacitance (each side)
Horizontal coupling capacitance (each side)
0.05 fF/mm2
0.03 fF/mm
0.01 fF/mm
0.03
Source: M. Bohr and Y. El-Mansy - IEEE TED Vol. 4, March 1998
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Integrated Circuit Wiring
Metal 5
Metal 4
Metal 3
Metal 2
Metal 1
Substrate
Vertical parallel-plate capacitance
Vertical parallel-plate capacitance (min width)
Vertical fringing capacitance (each side)
Horizontal coupling capacitance (each side)
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0.05 fF/mm2
0.03 fF/mm
0.01 fF/mm
0.03
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Chip-Level Interconnect Delay
Pulse Characteristics:
Line Characteristics
rise time: 100 ps
fall time: 100 ps
pulse width: 4ns
length : 3 mm
near end termination: 50 W
far end termination 65 W
Near End Response
Far End Response
1
0.7
0.6
Volts
0.45
Logic
threshold
0.175
Board
VLSI
Submicron
Deep Submicron
0.5
Volts
Board
VLSI
Submicron
Deep Submicron
0.725
0.4
0.3
Logic
threshold
0.2
0.1
0
-0.1
-0.1
0
0.4
0.8
1.2
1.6
2
0
T ime (ns)
0.4
0.8
1.2
1.6
2
T ime (ns)
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Package-Level Complexity
- Up to 16 layers
- Hundreds of vias
- Thousands of TLs
- High density
- Nonuniformity
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Signal Integrity
Ideal
Common
Noisy
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Signal Integrity
Crosstalk
Dispersion
Attenuation
Reflection
Distortion
Loss
Delta I Noise
Ground Bounce
Radiation
Drive Line
Sense Line
Drive Line
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IC on Package
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Mixed Signal Noise

Simultaneous switching and inductance (Leff)

Leff is f( current magnitude and direction)

Interactions between noise generated by power/ground and signal paths
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Power-Supply Noise
- Power-supply-level fluctuations
- Delta-I noise
- Simultaneous switching noise (SSN)
- Ground bounce
VOH
VOL
Actual
Vout
Ideal
Vout
Time
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Power Distribution Problem
Differential voltage
at receiver
V1 - R
Gate A
Low Frequency
+
+
Wire B
V1
Gate C
+
R
-
V1
N
-
-
Internal
reference
generator
GROUND CONNECTION
Output voltage from
Gate A
Differential voltage
at receiver
V2 - N - R
Gate A
High Frequency
+
V1
N
GROUND CONNECTION
Output voltage from
Gate A
+
Wire B
- +
Gate C
+
R
-
V2
-
Internal
reference
generator
Equivalent noise
source in series
with ground connection
At high frequencies, Wire B is a transmission line and
ground connection is no longer the reference voltage
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On-Chip Power and Ground Distribution
• Distribution Network for Peripheral Bonding
– Power and ground are brought onto the chip via bond pads located
along the four edges
– Metal buses provide routing from the edges to the remainder of the chip
Local Buses
VP Bus
GND
GND Bus
VP Bus
GND Bus
Wiring Tracks
VP Bus
VP
GND Bus
VP Bus
GND Bus
VP Bus
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Dual-in-Line (DIP) Package
-Mounted on PWB in pin-through-hole (PTH) configuration
- Chip occupies less than 20% of total space
- Lead frame with large inductance
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Packages & Packaging Trends
Thermal Package
Quad Flat Pack
MCM
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Stacked Wire Bonds
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Ceramic Substrate
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Area Bonding with Flip Chip
Bumped Die
Package
Body
Pins
– Minimizes IR drops between gates
– Minimizes interconnection inductance
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3D IC and TSV
Make use of third dimension
Can scale several orders of magnitude
(10/cm2 to 108/cm2)
Minimize interconnection length  reduce
delay
More design flexibility
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3D Integration
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Thru Silicon Vias
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TSV-Based Products
STMicro CMOS
image sensor in
WLP/TSV package
Sony Video / DSC
camera with BSI
CMOS image
sensors
Elpida’s 3D TSV stacked DRAM memory
There are currently about 15 different 3D-IC pilot lines
worldwide
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TSV and 3D-IC
Advantages
 Make use of third dimension
 Can scale several orders of magnitude (10/cm2 to 108/cm2)
 Minimize interconnection length  reduce delay
 More design flexibility
New Architectures
Issues
 3D Infrastructure & supply chain
 I/O Standardization
 EMI
 Thermal management and reliability
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- Memory
- Logic
- Analog
- MEMS
Silicon Interposer
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Silicon Interposer
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Measurements
VNA: S-parameter
Spectrum Analyzer
Time-domain simulation
Eye diagram
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Tools for Physical Design
* Schematic editor
* Netlist extractor
* Circuit level simulator
* Layout vs Schematic
* Layout editor
* Libraries
* Placement & routing
* Design verification
* Design rule checker
* Electromagnetic analysis
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State-of-the-Art in Extraction
CAPACITANCE
INDUCTANCE
* MoM- BEM
* MoM- BEM (2D)
* FEM
* FEM (2D)
* Fast Multipole
* PEEC (3D)
* Fast Multipole
Main Challenge: 3D inductance extraction is computationally
expensive.
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Circuit Simulation
Chip
Board/Module
Y(t) v(t) = I(t)
Given, Y and I, find v
* SPICE
* Asymptotic Waveform Evaluation
* Complex Frequency Hopping
* Passive Multipoint Matching Method
* Latency Insertion Method
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Why SPICE ?
 Established platform
 Powerful engine
 Source code available for free
 Extensive libraries of devices
 New device installation procedure straightforward
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SPICE
Directory Structure
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Interconnect Simulation Application
• New Interconnects:
– 3D Interconnect (System In Package)
– package-intermediated interconnects
Chip-Package-Board Co-Design
• Power Ground Network:
It will greatly affect the performance of the chip
design:
– Voltage (IR) drops on VDD nets
– ground bounce on VSS nets
– High currents in the power grids  Electromigration effect
Power Ground Network Design
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Chip-Package Co-Design
Repeated
Simulation of the
Package/Board
Super Fast
Simulation
Source: Joel Mcgrath, “Chip/package co-design: The bridge between chips and systems “,
Advanced Packaging Magazine June, 2001
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Power Ground Network Design Flow
Repeated
Simulation
of the P/G
network
 Super
Fast
Simulation
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Deep Submicron Timing Closure
Unbounded design iterations resulting from
unpredicted timing violations
- 0.25 microns and lower
- 2 to 20 iterations
- mismatch between logic and physical designs
- greater timing variations
- dominated by interconnects
- inductive and capacitive coupling
- slows time-to-market
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Example: Power Bus/Ground Plane Model
-
+
-
+
Unit cell
-
-
-
+
+
-
+
+
=
-
+
Modeling
- Determine R,L,G,C parameters and define cell
- Synthesize 2-D circuit model for ground plane
- Use SPICE to simulate transient
Typical workstation simulation time
for a 1200-cell network is 2 h 40 min.
Too time consuming!
Y cells
X cells
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Model Order Reduction
Large Network
(>1,000 nodes)
SPICE
Y(t) v(t) = i(t)
Reduced Order
Model
(< 30 poles)
Y() V() = I()
MOR Schemes
Order Reduction
~
Y() =~ Y()
• AWE
• Complex frequency hopping
• Padé via Lanczos
Recursive Convolution
~
Y(t) v(t) = i(t)
• Direct rational approximation
• Vector Fitting
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Latency Insertion Method (LIM)
• Fast Circuit Simulation Method




Has been used to simulate on-chip PDN Network
Simulates IR drop on deep submicron IC
Perfectly suited to model TSVs
Alternative to (slow) SPICE engine for large circuit size
No of
Nodes
20,000
30,000
40,000
50,000
SPICE
(sec)
1224
2935
4741
7358
LIM
(sec)
9
13
17
21
Speedup
136
225
278
350
Simplified view of an on-chip PDN
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X-Parameter Modeling of High-Speed Links
Time-Domain Response
8
Vin
Vout
6
4
Volts
2
X-Parameter
0
-2
-4
-6
SER
DES
-8
0
0.5
1
1.5
2
2.5
time(ns)
3
3.5
4
4.5
5
7
6
5
4
3
Vout, V
Vin, V
2
1
ADS
0
-1
-2
-3
-4
-5
-6
-7
25.0
25.2
25.4
25.6
25.8
26.0
26.2
26.4
26.6
26.8
27.0
27.2
27.4
27.6
27.8
28.0
28.2
28.4
28.6
28.8
29.0
29.2
29.4
29.6
29.8
30.0
time, nsec
• Simulation using X Parameters (Schutt-Aine – 2010)





Models nonlinear networks using harmonics
Superset of S-parameters
Can be measured using NVNA
First to demonstrate use for HSLINKs
Collaborating with Agilent for channel simulation
X-Parameters is a registered trademark of Agilent Technologies, Inc.
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