Transcript Large-Scale Performance Modeling of Analog and

Bayesian Model Fusion: Large-Scale
Performance Modeling of Analog and MixedSignal Circuits by Reusing Early-Stage Data
Fa Wang*, Wangyang Zhang*, Shupeng Sun*, Xin Li*, Chenjie Gu┼
*ECE Dept. Carnegie Mellon University, Pittsburgh, PA 15213
┼ Intel Corp. Hillsboro, OR 97124
Slide 1
Outline




Background
Bayesian Model Fusion
Experiment Results
Conclusion
Slide 2
Process Variations and Performance Modeling
65nm
45nm
32nm
Small Size
Large Variation

Statistical performance modeling: approximate circuit
performance as an analytical function of process variations
f X   1  g1 X    2  g 2 X      N  g N X 
f:
circuit performance of interest (e.g. read delay of SRAM)
∆X:
a vector of random variables to model process variations
gi(∆X): basis functions (e.g., linear or quadratic polynomials)
αi:
model coefficients

Performance model is a powerful tool for efficient circuit
analysis:



Yield estimation
Corner extraction
Sensitivity analysis
Slide 3
Solving Performance Model: Least Squares Fitting (LSF)

Determine performance model

LSF
 1 
Performance  f (X )   am g m (X )  g1 (X ), g 2 (X ),...g M (X )   
m
 M 
Basis functions
Model
coefficients
A set of sampling points are collected
 Model coefficients are solved from the following linear equation

Total of M basis
 f (1)   g1 (X (1) ) g 2 (X (1) )
 ( 2)  
( 2)
( 2)
g
(

X
)
g
(

X
)
f
1
2


   


 (K )  
(K )
(K )
 f   g1 (X ) g 2 (X )
Basis 1
Basis 2

 g M (X (1) )   1 
  
 g M (X ( 2) )    2 


  



(K )  
 g M (X )  M 
Basis M
Total of K
MC samples
The problem is required to be over-determined in order to be
solvable (i.e. K > M)
Slide 4
Challenge: High Dimensionality

High dimensionality becomes a challenge in performance
modeling
Large number of independent random variables must be used to
describe variations in each transistor
 Increased number of transistors in circuits


Example: a commercial 32nm CMOS process

~40 random variables to model mismatches of a single transistor
Circuit
Transistor #
Random variable #
Operational amplifier
~ 50
~ 2000
SRAM critical path
~ 10K
~ 400K

Due to high dimensionality (i.e. large # of basis functions), it’s
unrealistic to apply LSF (which requires # of MC samples> #
of basis functions)
Slide 5
Sparsity




To handle the high dimensionality problem, sparsity feature of
circuits has been explored[1]
Sparsity means that the circuit performance variability is only
dominated by a few random variables
Example: In SRAM critical path, many Vth mismatches of
transistors are not important
M
Performance model f (X )   am g m (X ) has a sparse profile:
m 1

Most of coefficients an are zero or close to zero
 a1 
a 
f (X )  [ g1 (X ), g 2 (X ),..., g M (X )] 2 
  
 
 aM 
Performance
Model coefficients
Basis functions
[1] X. Li, "Finding deterministic solution from underdetermined equation: large-scale performance modeling of
Slide 6
analog/RF circuits," TCAD, vol. 29, no. 11, pp. 1661-1668, Nov. 2010
Sparse Regression

Sparse regression algorithm is an efficient performance
modeling algorithm that utilizes the sparsity feature

Sparse regression is better than LSF because it requires less
number of samples by using sparsity feature

Efficiency of performance modeling can be further improved,
by considering additional information from design flow (will
be discussed in detail later)
Slide 7
Outline




Background
Bayesian Model Fusion
Experiment Results
Conclusion
Slide 8
Bayesian Model Fusion (BMF): Overview

Key idea: BMF facilitates late stage performance modeling by
reusing data collected in the early stage
Traditional
Performance modeling
Performance modeling
Early stage
data
Late stage
data
Performance modeling
BMF
Proposed
Slide 9
AMS Circuit Design Flow

Analog and mixed-signal (AMS) circuit design spans multiple stages
Design cycle for analog and mixed-signal circuits
Early stage
Schematic
design stage
Performance
modeling
…
Late stage
Layout
design stage
…
Performance
modeling
…
Circuit modeling
Slide 10
Correlation in AMS Design Flow

One important fact in AMS design flow is that different stages
share the same circuit topology and functionality
Comparator:
Schematic stage

Layout stage
Leads to correlation among different stages
Slide 11
Correlation in Performance Models
f E X    E1  g1 X    E 2  g 2 X      EN  g N X 
f L X    L1  g1 X    L 2  g 2 X      LN  g N X 
fE(∆X):
fL(∆X):
αEi, αLi :
gi(∆X):

early-stage performance model
late-stage performance model
model coefficients
basis functions
Correlation: fE(∆X) and fL(∆X) are “likely” to be similar
fE(∆X)
g1(∆X)
g2(∆X)
g3(∆X)
g4(∆X)
αE1
αE2
αE3
αE4
…
fL(∆X) αL1  αE1 αL2  αE2 αL3  αE3 αL4  αE4 …
Slide 12
The Proposed Algorithm Flow
Early stage data
Very few late stage data
Prior
Early stage
performance model
f E x  
M

E ,m
Bayesian inference
(Proposed)
f L x  
 g m x 
Likelihood
M

L, m
 g m x 
m 1
m 1
Late stage performance model
Early stage
Late stage
Slide 13
Prior


Prior is a distribution that describes the uncertainty of
parameters based on early stage data, before late stage data
is taken into account
In our work, information in early design stage is encoded in
prior, which describes the uncertainty of late stage model
coefficients
pdf(αL,m)
Prior distribution
αL,m1
αL,m2
Higher
Probability
Lower
Probability
Slide 14
Prior

Magnitude information of early-stage model coefficients is
encoded in prior
Magnitude information here describes whether the absolute
value of coefficient is relatively large or small
 Small (or zero) coefficients information represents sparsity
profile, which is essential for performance model[1]


Define prior distribution as a zero-mean Gaussian distribution

Key idea of encoding: the shape of prior is related to magnitude
information
PDF
pdf(αL,1) ~ N(0, 12)
Prior distribution
pdf(αL,2) ~ N(0, 22)
0
αL,1 or αL,2
[1] X. Li, "Finding deterministic solution from underdetermined equation: large-scale performance modeling of
Slide 15
analog/RF circuits," TCAD, vol. 29, no. 11, pp. 1661-1668, Nov. 2010
Likelihood


Likelihood is a function of parameters, which evaluates how
parameters fit with data
Late stage information is encoded in likelihood function
Specifically, late stage performance function information is
encoded in likelihood function
 In our work, likelihood function describes how well model
coefficients fit with late stage data

likelihood(αL,m)
Likelihood
αL,m1
αL,m2
Better fit
Worse fit
Slide 16
Maximum-A-Posteriori Estimation

However, if we determine model coefficients solely based on
likelihood, we may have over-fitting problem


In our case, # of samples in late stage is smaller than # of model
coefficients in late stage
Bayesian’s theorem
p( L | FL )  p( L ) p( FL |  L )
Posterior

Prior
Likelihood
p( L | FL )
Maximum-a-posteriori (MAP) estimation: max
aL
pdf(αL)
MAP estimation of αL
likelihood(αL)


Prior distribution
Likelihood
Posterior
Slide 17
Outline




Background
Bayesian Model Fusion
Experiment Results
Conclusion
Slide 18
SRAM Example

Example 1: CMOS SRAM
Designed in a commercial 32nm SOI
 61572 independent random process parameters are considered
 Read delay is considered as performance
 Linear performance model is fitted
 Experiments run on a 2.5GHz Linux server with 16GB memory

Cell array
Timing logic
WL
Sense amp
Out
Slide 19
Modeling Error

Two different methods are compared:
The proposed method (BMF)
 Orthogonal Matching Pursuit (OMP)

Modeling error
Modeling Error (%)

4
OMP (Traditional)
BMF (Proposed)
3
2
4x
1
0
200
400
600
800
Number of Post-Layout Samples
Slide 20
Modeling Time Speed-up

BMF requires 4x less samples to achieve similar accuracy as
OMP in SRAM

4x runtime speed-up to build performance model
OMP
(Traditional)
400
BMF
(Proposed)
100
Read delay error
1.02%
0.99%
Simulation cost (Hour)
38.77
9.69
Fitting cost (Second)
3.56
2.11
Total modeling cost (Hour)
38.77
9.69
Post-layout samples
Slide 21
RO Example

Example 2: CMOS ring oscillator
Designed in a commercial 32nm SOI
 7177 independent random process parameters are considered
 Power, frequency and phase noise are considered as performance
 Linear performance model is fitted
 Experiments run on a 2.5GHz Linux server with 16GB memory

Slide 22

Modeling error is measured
for power, frequency and
phase noise
Modeling Error (%)
Modeling Error
3
OMP (Traditional)
BMF (Proposed)
2
Power
9x
1
0
2
1.5
1
OMP (Traditional)
BMF (Proposed)
Frequency
9x
0.5
0
200 400 600 800
Number of Post-Layout Samples
Modeling Error (%)
Modeling Error (%)
200
400
600
800
Number of Post-Layout Samples
0.3
0.2
OMP (Traditional)
BMF (Proposed)
9x
Phase noise
0.1
0
200 400 600 800
Number of Post-Layout Samples
Slide 23
Modeling Time Speed-up

BMF requires 9x less samples to achieve similar accuracy as
OMP in RO

9x runtime speed-up to build performance model
OMP
(Traditional)
900
BMF
(Proposed)
100
Power error
0.77%
0.72%
Frequency error
0.65%
0.54%
Phase noise error
0.12%
0.12%
Simulation cost (Hour)
12.58
1.40
Fitting cost (Second)
5.75
1.69
Total modeling cost (Hour)
12.58
1.40
Post-layout samples
Slide 24
Conclusion



The proposed BMF method facilitates efficient highdimensional performance modeling at late stage by reusing
early stage data
BMF achieves more than 4x runtime speedup over traditional
OMP method on SRAM and RO test cases
BMF can be used for commercial applications such as macromodeling based verification
Slide 25