Transcript Lecture Notes on ``SRAM/DRAM Memory`` (PPT Slides)

ENG241
Digital Design
Week #11
Memory Systems
Week #11 Topics
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Random Access Memory
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Static RAM
Array of RAM ICs
Dynamic RAM
Types of Dynamic RAM
Comparison
Larger Wider Memories
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Resources
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Chapter #9, Mano Sections
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9.1
9.2
9.3
9.4
9.5
9.6
Memory Definitions
Random Access Memory
SRAM Integrated Circuits
Array of SRAM ICs
DRAM ICs
DRAM Types
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A Digital Computer System
Data/Instructions/code
Memory
clock
CPU
Inputs:
Keyboard,
mouse, modem,
microphone
Control
unit
Datapath
Input/Output
Outputs: CRT,
LCD, modem,
speakers
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Picture of Memory
•
You can think of memory as being one big array
of data.
– The address serves as an array index.
– Each address refers to one word of data.
•
You can read or modify the data at any given
memory address, just like you can read or
modify the contents of an array at any given
index.
Address
00000000
00000001
00000002
.
.
.
.
.
.
.
.
.
.
FFFFFFFD
FFFFFFFE
FFFFFFFF
Data
Word
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Memory Signal Types
•
Memory signals fall into three groups
– Address bus - selects one of memory locations
– Data bus
• Read: the selected location’s stored data is put on the data bus
• Write (RAM): The data on the data bus is stored into the selected
location
– Control signals - specifies what the memory is to do
• Control signals are usually active low
• Most common signals are:
– CS: Chip Select; must be active to do anything
– OE: Output Enable; active to read data
– WR: Write; active to write data
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Properties of Memory
1. Volatile: Memory contents
disappears if power turned off
 Typical computer RAM
 PDA, Smart Phone, iPADs, …
2. Nonvolatile: Contents of memory
remain even if power turned off
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ROM
PROM, EEPROM
Flash memories
Magnetic memories like disk, tape
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Memories in General
Computers have two types of memory
1. Volatile Memory
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RAM (Random Access Memory)
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2.
Static RAM usually used for Cache
Dynamic RAM used for Main Memory
Non-Volatile Memory
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ROM (Read Only Memory), FLASH
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Used to store permanent programs in a
computer system (booting)
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Classification of Memory
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Key Design Metrics
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Memory Hierarchy
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The design constraints on a computer memory can be summed up by
three questions (i) How Much (ii) How Fast (iii) How expensive.
There is a tradeoff among the three key characteristics
A variety of technologies are used to implement memory system
Dilemma facing designer is clear  large capacity, fast, low cost!!
Solution  Employ memory hierarchy
Flip Flops
Cache
Dynamic RAM
Cost
registers
Static RAM
Capacity
Main Memory
Disk Cache
Magnetic Disk
Access
Time
Removable Media
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Main Memory vs. Cache
Dynamic RAM
Static RAM
Registers
Static RAM
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Memory
Registers
Static RAM
CPU
Cache
Controller
PCI
Controller
Cache
Memory
Local CPU / Memory Bus
DRAM
Dynamic RAM
Co-processor
Peripheral Component Interconnect Bus
EISA/PCI Bridge
Controller
Hard Drive
Controller
Video
Adaptor
SCSI
Adaptor
EISA PC Bus
SCSI
Bus
PC Card 1
PC Card 2
PC Card 3
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RAM vs. ROM
o
RAM
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Read/write
Volatile
Faster access time
Variants
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SRAM
DRAM
Application
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ROM
Variables
Dynamic memory
allocation
Heaps, stacks
Read only
Non-Volatile
Slower
Variants
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PROM,EPROM
EEPROM, FLASH
Application
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Programs
Constants
Codes, e.t.c
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Random Access Memories
o
o
So called because it takes the same
amount of time to address any
particular part
Types of RAM
1.
2.
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Static RAM (SRAM), fast, expensive
Dynamic RAM (DRAM), slow, cheap
How is memory accessed?
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Address Lines, Data Lines
Control Signals (R/W, chip select, …)
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Simple View of RAM
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o
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Of some word size n=4,8,16 ….
Some capacity 2k
k bits of address line, k=10,11,..
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Has a read line
Has a write line
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1K x 16 memory
o
o
o
o
Variety of sizes
 From 1-bit wide
Issue is no. of pins
Memory size specified in bytes
 1K x 16 bit  2KB memory
10 address lines and 16 data lines
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Chip Select and R/W Lines
o
o
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R/W Lines enable reading/writing
Usually a chip select line is used.
Why?
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To enable RAM chip to be accessed.
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Memory: Writing
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Sequence of steps
Setup address lines
 Setup data lines
 Activate write line (maybe a pos edge)
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The write cycle time is the maximum
time from the application of the
address to the completion of all
internal memory operations required to
store a word.
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Writing: Timing Waveforms
o
o
CPU operates at 50 MHz (20 ns)
4 clock cycles to perform a write
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Memory Reading
o Steps
Setup address lines
Activate read line
Data available after specified amount of
time
o Read cycle usually is shorter than
write cycle.
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Memory Waveform: Reading
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CPU operates at 50 MHz (20 ns)
65 ns required for a read cycle
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Static RAM: 4T and 6T
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Static RAM: Internal Structure
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Simplify Modeling using Latch
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o
o
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•
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Storage is modeled by an SR latch.
Control logic
One memory cell per bit
For select = 0, the stored
content is held.
For select = 1, the stored
content is determined by
values on B and B’
The outputs are gated by the
select line also.
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Bit Slice
o Cells connected to form 1
bit position
o Word Select gates one
latch from address lines
o Note it selects Reads also
o B (and B’) set by R/W,
Data In and BitSelect
o When R/W = 0 and
BitSelect = 1, then if Data
in = 1  the latch will be
set (i.e. a 1 is written)
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Bit Slice can Become Module
o
o
Basically bit slice is a one
Dimensional array of memory
What type of hardware do we
need to access one row at a
time?
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16 X 1 RAM
o
o
o
4 address lines
required to access
16 locations.
A Decoder is added
to select the
different words
(each 1 bit wide).
For 16 words we
need a 4-to-16 line
Decoder
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Row/Column
o
o
o
o
Practical memories contains thousands of
words!!
If RAM gets large, there is a huge decoder
Also run into chip layout issues
How can we change the structure of
Memory to solve this problem?
o
Rearrange the memory into “2D” i.e., matrix
layout
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16 X 1 as 4 X 4 Array
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Two decoders
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•
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Row
Column
Address just
broken up
Not visible
from outside
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16 X 1 as 4 X 4 Array
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o
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Employing 2
decoders instead of
1 row decoder is
called coincident
selection
Row Select and
Column Select
A3A2A1A0=0000 will
attempt to choose
RAM cell 0.
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Change from 16x1 to 8 X 2 RAM
o
o
o
Minor change in
logic
Try addressing
011 on board
Cells 6,7 are
chosen for
reading or
writing.
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A Single Row Decoder
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Imagine 32k x 8 = 256K bit memory
o
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15 address lines are required (for 32K)
One column layout would need 15-bit
decoder with 32,768 outputs
For a single decoder that would mean 32,800
gates
 This is not practical!
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o
How about coincident selection?
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Coincident Selection
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o
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A 32K X 8 contains 256 Kbits
A 15 bit address line is required.
To make the number of rows and columns equal we
take the square root of 256K, giving 512 = 29
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o
For the columns 512/8 = 64 = 26
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A 9-to-512 decoder is required for the rows (9 address
lines are fed to the Row Decoder).
Remember we need 8 bits of output!! (Column Decoder?)
A 6-to-64 line decoder is required for the columns (6
address lines are fed to the Column Decoder).
Total number of gates is 512 + 64 = 576 (i.e.
reducing the total gate count by more than 50!)
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SRAM Performance
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o
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Current SRAMs have cycle times in low
nanoseconds (say 2.5ns)
Used as cache (typically on-chip or offchip secondary cache)
Sizes up to 256 Mbit or so for fast chips
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Larger/Wider Memories
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Made up from sets of chips
Consider a 64K by 8 RAM
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Note new symbols for sets of lines, 8 & 16 bits
wide
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Larger: 256k x 8
Connect all output data
lines together (tristate)
 Connect all input data line
together
 16 lines of address to fetch
a word in any DRAM chip
How to select the specific
RAM chip?
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Larger Capacity
o
Decoder for highorder 2 bits
Selects chip
 Look at selection
logic
 Address ranges
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Wider Memory – 64K X 16
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Dynamic memory
•
Dynamic memory is built with capacitors.
– A stored charge on the capacitor represents a logical 1.
– No charge represents a logic 0.
•
However, capacitors lose their charge after a few milliseconds. The
memory requires constant refreshing to recharge the capacitors.
(That’s what’s “dynamic” about it.)
•
Dynamic RAMs tend to be physically smaller than static RAMs.
– A single bit of data can be stored with just one capacitor and one
transistor, while static RAM cells typically require 4-6 transistors.
– This means dynamic RAM is cheaper and denser—more bits can be
stored in the same physical area.
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Dynamic RAM
o
o
Capacitor can hold charge
Transistor acts as gate
No charge is a 0
 Can close switch & add charge to
store a 1
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o
Then open switch (disconnect)
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DRAM Cell
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DRAM read operations
–
–
–
–
–
Precharge bit line to VDD/2.
Take the word line HIGH.
Detect whether current flows into or out of the cell.
Note: cell contents are destroyed by the read!
Must write the bit value back after reading.
DRAM write operations
– Take the word line HIGH.
– Set the bit line LOW or HIGH to store 0 or 1.
– Take the word line LOW.
– Note: The stored charge for a 1 will eventually leak off.
Dynamic RAM (… continued)
Select
T
B
Stored 0
Stored 1
To Pump
C
DRAM cell
(a)
(b)
(c)
Write 1
(d)
(e)
Read 1
(f)
Write 0
Read 0
(g)
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DRAM Characteristics (Why Slow!)
o
Destructive Read
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Refresh
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When cell read, charge removed
Charge must be restored after a read
Capacitors are not perfect! there’s steady leakage
Charge must be restored periodically
DRAM are dense (lots of cells) so there are
many address lines.
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To reduce the physical size of DRAM we can
reduce the number of pins by applying the
address lines serially in two parts:
•
•
Row Address, and then
Column Address
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How DRAM Works
A7A6A5A4A3A2A1A0
A7A6A5A4
A3A2A1A0
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DRAM-chip internal organization
64K x 1
DRAM
DRAM charge leakage
• Typical devices require each cell to be
refreshed once every 4 to 64 mS.
DRAM Logic Diagram
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DRAM Read Signaling
o
DRAM has a lower pin count by using same pins
for row and column addresses
Delay until
data
available
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DRAM Write Timing
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DRAM Refresh
o
o
o
o
Many strategies
Logic on chip
Refresh counter and
Refresh controller
Refresh counter is
used to provide the
address of the row of
DRAM cell to be
refreshed.
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CAS Before RAS
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o
o
o
Set column address
Apply CAS first (opposite of RW)
Then toggle RAS enough times to cycle through row
addresses
On-board refresh counter applies the row addresses
CAS
RAS
Col Add
Row Add
Row Add
Row Add
Row Add
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DRAM Chip Types
DRAM
FPM RAM
EDO RAM
BEDO RAM
SDRAM
DDRRAM
- Dynamic RAM
- Fast page-mode RAM
- Extended Data Out RAM
- Burst Extended-data-out RAM
- Synchronous Dynamic RAM
- Double Data Rate RAM
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Page Mode DRAM
o
o
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DRAMs made to read & write blocks
Example
 Assert RAS, leave asserted
 Assert CAS multiple times to read sequence of
data
Similar for writes
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Synchronous DRAM (SDRAM)
o
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Double Data
Rate SDRAM
Transfers
data on both
edges of the
clock
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DRAM Evolution
There has been multiple improvements to the DRAM
design in the past 20 years.
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SDRAM: A clock signal was added making the design
synchronous.
DDR SDRAM: The data bus transfers data on both rising
and falling edge of the clock.
DDR2 SDRAM: Second generation of DDR memory scales
to higher clock frequencies.
DDR3 SDRAM: Third generation has lower power
consumption, higher clock frequency and denser modules
DDR4 SDRAM: Fourth generation, improvement over
DDR3, high bandwidth, higher speed. However it is not
compatible with any earlier type of (RAM) due to different
signaling voltages.
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DDR SDRAM Comparison
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Memory Technologies
o
o
DRAM: Dynamic Random Access Memory
 upside: very dense (1 transistor per bit) and
inexpensive
 downside: requires refresh and often not the
fastest access times
 often used for main memories
SRAM: Static Random Access Memory
 upside: fast and no refresh required
 downside: not so dense and not so cheap
 often used for caches
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Summary
o
RAMs with different characteristics
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o
For different purposes
Static RAM
Simple to use, small, expensive
 Fast, used for cache
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Dynamic RAM
Complex to interface, largest, cheap
 Needs periodic refresh
 Dense, slow, used in Main Memory
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Links
Ram Guides (not very technical)

http://arstechnica.com/paedia/storage.html
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