Transcript FE-TC4-DS - indico in2p3

5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
DEVELOPMENTS
ON ATLAS PIXEL
DETECTORS
Patrick Pangaud
Centre de Physique des Particules de Marseille
C.P.P.M
163, avenue de Luminy
Case 902
13288 Marseille cedex 09
France
[email protected]
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5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
OUTLINE
Hybrid Pixels Detector for High Energy Physics
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Atlas developments
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•
•
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IBM 130nm : FE-I4 development
TSMC 65nm : FE-x5 developments
TEZZARON 3-D 130nm: FE-TC4 developments
Global Foundries 130nm : FE-C4 developments
Monolithic Pixels Detector for High Energy Physics
•
Smart pixel (monolithic)
•
Global Foundries 130nm : HV-CMOS development
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5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
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Hybrid Pixels Detector
for particles trackers
An early 3-D approach!!
• Sensor for particles detection
• Dedicated electronic chip
AND
• A bump-bonding solder for
interconnection

Sensors (Si, CdTe, GaAs, Diamond…) for
ionizing particles
Electronic pixel readout




Monolithic device
Analog detection (low noise, low power)
Discriminator
Digital readout
5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
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Hybrid Pixels Detector
for LHC/HL-LHC at CERN
Whatever will be discovered in next years
at LHC, need much data to understand
what has been discovered.
Higher luminosity allows extending
discovery/studies to
• higher masses
• processes of lower cross-section
LHC has plans of upgrade by increasing
luminosity to collect ultimately ~ 3000 fb-1 .
This will open new physics possibilities.
LHC : Luminosity of 1034 cm-2.s-1
HL-LHC expected 10 times more luminosity, more
pixels, more ionizing particles, more … !!!
5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
LHC and ATLAS upgrade
Possible upgrade timeline
→14 TeV
→ 5x1034cm-2s-1
luminosity leveling
∫ L dt
7 TeV
1x1034 →
~2x1034cm-2s-1
3000 fb-1
phase-2
→ 1x1034cm-2s-1
1027 →
2x1033cm-2s-1
~300 fb-1
phase-1
~50 fb-1
phase-0
~10 fb-1
2013/14
Now
T. Kawamoto, TIPP2011, Chicago, USA
2018
~2022
Year
ATLAS needs to maintain excellent
position resolution (vertexing, tracking)
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5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
Inner Tracking ATLAS detector
Straw tubes
Silicon strip
Silicon pixel
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5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
HYBRID PIXELS SENSOR
FOR HIGH ENERGY PHYSICS
IBM 130nm
FE-I4 development
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5th FCPPL Workshop , Orsay-Saclay March 23, 2012
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ATLAS upgrade : phase - 0
IBL technology
• Planner silicon sensor
• 3-D silicon sensor
• Diamond sensor → postponed for future upgrade
Existing B-layer
Newbeam pipe
IBL mounted on beam pipe
New readout chip
of higher performance
Double side 3D sensor
Planner sensor prototype
T. Kawamoto, TIPP2011, Chicago, USA
5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
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50 μm
Hybrid Pixels Sensor for HEP
The FE-I4 readout chip
FE-I3 CMOS
technology : 250 nm
Done : ATLAS/LHC
(2008/2009)
50 μm
400 μm
FE-I4 CMOS
technology : 130 nm
250 μm
Under Production
ATLAS/LHC upgrade project
(2013-2014)
• Participating institutes:
FE-I3
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160
FE-I4
Bonn: D. Arutinov, M. Barbero, T. Hemperek,
A. Kruth, M. Karagounis.
CPPM: D. Fougeron, M. Menouni.
Genova: R. Beccherle, G. Darbo.
LBNL: S. Dube, D. Elledge, M. Garcia-Sciveres,
D. Gnani, A. Mekkaoui.
Nikhef: V. Gromov, R. Kluit, J.D. Schipper
5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
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FE-I4 : Motivation for Redesign of FE
• Need for a new FE?
FE-I3FE-I4
• Smaller b-layer radius + potential luminosity increase
architecture saturated.
FE-I3 at r=3.7 cm!
FE-I4 new digital architecture:
EOC
sLHC
80
IBL
FE-I3 column-drain
100
60
40
20
LHC
Inefficiency [%]
higher hit rate.
0
0
local regional memories,
stop moving hits around (unless RO).
FE-I4 has smaller pixel
0.25 μm130 nm
(reduced cross-section).
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2
3
4
5
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7
8
9
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Hit prob. / DC
The “inefficiency wall”
• New technology: Higher integration density for digital circuits, rad-hard, availibility.
M. Backhaus, FEI4 course, Desy, Germany
5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
HYBRID PIXELS SENSOR
FOR HIGH ENERGY PHYSICS
TSMC 65nm
FE-x5 development
TEZZARON 3-D AND GLOBAL FOUNDRIES 130nm
FE-TC4 development
FE-C4 development
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5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
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Motivations for
ATLAS read-out chip upgrades – Phases 1 and 2
• Improve spatial resolution
• Deal with an increasing counting rate
50 μm
• Decrease pixel size
FE-I3 ,
250 nm
400 μm
25 μm
FE-I4 ,
130nm
250 μm
100 μm
Vertical stacking
50 μm
50 μm
Technology shrinking
FE-x5 ,
65nm
First MPW run for High Energy Physics organized by
FNAL with a consortium of 15 institutes.
The proposed 3-D process combines :
GLOBAL FOUNDRY 130nm technology
TEZZARON 3D technology
ANALOG
DIGITAL
FE-TC4 ,
130 nm
125 μm
3-D benefits :
Pixel size reduction
Functionalities splitting
Technologies mixing
5th FCPPL Workshop , Orsay-Saclay March 23, 2012
65nm technology -> FE-x5
Patrick Pangaud - CPPM-IN2P3-CNRS
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5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
Tezzaron-Chartered
3-D technology
Main characteristics :

2 wafers (tier 1 and tier 2) are
stacked face to face with CuCu thermo-compression bonding

Via Middle technology :
Super-Contacts (Through
Silicon contacts) are formed
before the BEOL of Chartered
technology.

Wafer is thinned to access
Super-Contacts

Chartered 130nm technology
limited to 5 metal levels

Back-side metal for bonding
(after thinning)
10µm
5µm
Wafer to wafer bonding
Bond interface
layout
Bond
M6
Interface
M5
M4
M3
M2
M1
1.2µm
12µm
2.5µm min
One tier
SuperContact
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5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
Fermilab 3-D Multi-Project Run
Fermilab
has planned a dedicated 3-D multi project run using Tezzaron for HEP
during 2009
There are 2 layers of electronics fabricated in the Global Foundries 0.13 um
process, using only one set of masks. (Useful reticule size 15.5 x 26 mm)
The wafers are bonded face to face.
ATLAS/HL-LHC
Sub-part
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5th FCPPL Workshop , Orsay-Saclay March 23, 2012
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Fermilab 3-D Multi-Project Run :
C-Band ATLAS
SEU-3D
SEU-3D
FE-TC4-AE
FE-TC4-DS
TSV Daisy Chain + BI
Electrical Test
TSV vs Transistors
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


Mechanical stress
DFF + Trans + Cap
Electrical Test
TSV vs Transistors
+ capacitors
FETC4-AE (CPPM) : same than FEC4_P1,
FETC4-DS (CPPM) : Shift Register + counter + readout data and ”Drum registers“
SEU-3D (CPPM) : SEUless memories blocks
General test structures (CPPM) : TSV + BI Daisy chain (electrical parameters) ; TSV capacitors value with and without BackMetal and
BI ; Transistors (Linear and ELT) closed to TSV ; Mechanical stress effects of devices (Trans, Cap, Res, DFF)
5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
Fermilab 3-D Multi-Project Run :
D-Band ATLAS
FE-TC4-AE
Electrical Test
TSV vs Transistors
TSV, Cap and Bump
OmegaPix
Analog
OmegaPix
Digital
FE-TC4-DC
Electrical Test
TSV vs Transistors
FETC4-AE (CPPM) : same than FEC4_P1
 FETC4-DC (Bonn-CPPM) : Digital pixels Read-out "à la FEI4“
 OmegaPix (LAL) : a 50x50 µm matrix pixel size
General test structures (CPPM) : TSV + BI Daisy chain (electrical parameters) ; TSV capacitors value with
and without BackMetal and BI ; Transistors (Linear and ELT) closed to TSV ; Mechanical stress effects of
devices (Trans, Cap, Res, DFF)

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5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
3-D project steps
Submission / Test
• First 3-D design (MPW organized by FNAL) FE-TC4_P1 project
• Global Foundries 130 nm (5 metal levels)
+ Tezzaron
• One Tier for the analogue pixel part :
• 14x61 pixel matrix
• Pixel size : 50x166µm
• One Tier for the digital part
• Two versions have been designed :
• one dedicated for test, (FE-TC4-DS)
• one “FE-I4-like”.,(FE-TC4-DC)
July 09 / now
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5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
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FE-TC4-AE analogue tier
Based on FE-C4_P1 chip + all adds for 3-D connection
Additional
switch for
read-out
Input signal from
sensor via the
Super-Contacts
Bonding pad in
Back-side metal
2 possible ways for discriminator
output read-out:
With the simple read-out part
existing yet into the pixel
With the tier 2 (via the Bond
Interface)
5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
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FE-TC4-DS digital tier for test :
parasitic coupling study between tiers
 Analogue tier and digital tier are face to
face (sensitive part facing digital part).
ANALOGUESuperContact
M1
M2
M3
M4
M5
 FE-TC4-DS : dedicated for parasitic
coupling studies between the 2 tiers.
M6
M6


Read the discriminator output
Generate noise (digital commutations)
in front of 11 specific areas of the
analogue pixel (preamplifier, feed-back,
amplifier2, DAC…)
Test different shielding configurations.
Analogue pixel layout :
11 specific areas
Tier 1
(thinned
wafer)
Bond Interface
M5
M4
M3
M2
M1
 3 functions :

Back Side
Metal for
bonding
Tier 2
DIGITAL
SuperContact
5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
FE-TC4-P1 test results : 3-D Chips
Mean Threshold versus dose
Mean Noise versus dose
3500
3000
60
FE-TC4_AE_2
FE-TC4_AE_1
2500
Mean Noise (e-)
Mean Threshold (e-)
4000
FE-TC4_AE_3
2000
1500
FE-C4_P1
1000
FE-C4_P1
40
FE-TC4_AE_2
FE-TC4_AE_1
FE-TC4_AE_3
30
20
10
500
0
0,1
50
1
10
Dose (MRad)
100
1000
0
0,1
1
10
100
1000
Dose (MRad)
We received individual tiers at the beginning of 2011. These individual tiers are not 3-D connected together.
The FETC4-AE analog tier has similar results as FEC4_P1 chip with radiation tolerance up to 240MRads.
The FETC4_DS and FETC4_DC digital tiers work (not irradiated at the moment).
The SEU-3D chip works well with protons radiation tolerance up to 400Mrads.
The full 3-D chips arrived during summer 2011. Two kinds of chips were tested.
The analog and digital tiers of the FETC4-AEDS and FETC4-AEDC chips work individually but no
data exchange have been demonstrated. The analog tier shows very good results. Untuned
Threshold dispersion value 226 e- and noise lower than 100 e-.
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5th FCPPL Workshop , Orsay-Saclay March 23, 2012
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The FE-TC4 ATLAS full-scale chip
• FE-TC4,
FE-I3
• Very large matrix size : 336 x 160
18
160
FE-TC4
run 3-D
160
pixels
Chip size of 18.8 x 20.1 mm.
1.95 mm End Of Column width.
• Small pixel size : 125µm x 50µm
• Bump bond pads compatible with
250 µm sensor pitch (FE-I4 project)
• The FE-TC4 re-uses main blocks of FEI4 to be compatible for sensors, bump
bonding , module/stave integration,
testing tools, software, mechanics
Thanks to W.Wei (IHEP) for his collaboration by helping the design ( improvement
of the pixel definition, global simulation by using Ultrasim and drafting the final
Matrix)
5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
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2-D Project steps
FEI4_P1 design : IBM 130nm, 8 metals
14x61 "analogue" pixel matrix
Pixel size : 50x166µm
Rad-hard and SEU tolerance
FEC4_P1 circuit : 2D Chartered 130nm, 8 metals
Submission / Test
March 08 / Summer 08
February 09 / April 09
Pixel structure : identical to FEI4_P1
(due to schedule no optimization has been
done)
Objectives : test Chartered technology (functionalities,
performances, radiation…)
FEC4_P2 circuit : 2D Chartered, 8 metals
Nov 09 / Jan 10
Based on FEC4_P1 circuit, plus :
Optimization of transistors
New latches for irradiation tests
New PadRing strategy and ground/substrate separation
FEC4_P3 : 2D Chartered, 8 metals but only 5 are used)
Smaller pixel size : 50µm x 125µm
Design of new sub-circuits and functionalities :
Analogue multiplexor and Triple redundancy memory
Calibration (pulse generator)
PLL
LVDS and ESD I/O Pads
Thanks to N. Wang, J.Luo, W.Wei (IHEP)for their collaborations
Nov 10 / Nov 11
5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
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FE-C4_Px test results
• All prototypes showed excellent results
• Un-tuned threshold dispersion around 200 e-
61x14 array
• Noise lower than 100 e- rms
• Power consumption 27µA/pixel
Control room
Irradiation
performed at
CERN/PS facility
(24 GeV protons)
Synchronization signals
from the machine
USB
link
DE2 board
Irradiation zone
LVDS to LVTTL translator
LVDS signals
Intermediate board
~20 meters
Irradiated
Sample
In the beam
Single ended
~4 meters
Outside the beam
Power Supply
Thanks to W.Zheng (IHEP) , Z.Lei (USTC) for their collaborations
5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
HYBRID PIXELS SENSOR
FOR HIGH ENERGY PHYSICS
GLOBAL FOUNDRY 130NM
HV-CMOS DEVELOPMENT
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5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
SMART Diode in CMOS technology
P-substrate
Pixel electronics in the deep n-well
Ivan Peric, FEE2011, Bergamo, Italy
Deep n-well
NMOS transistor
in its p-well
The sensor is based on the
depleted area between the “deep”
n-well and the p-substrate
PMOS transistor
E-field
Particle
The CMOS signal processing electronics are placed inside the deep-n-well. PMOS are placed directly
inside n-well, NMOS transistors are situated in their p-wells that are embedded in the n-well as well.
Expected signal : Mips of 2000e- ( by increasing the substrate resistivity)
Can we mix the smart diode and the 3D Integrated technology?
We will submit soon a 1st prototype smart pixels with the 3D Tezzaron-Global Foundries
Technology
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5th FCPPL Workshop , Orsay-Saclay March 23, 2012
Patrick Pangaud - CPPM-IN2P3-CNRS
Summary
• Since 20 years , the CPPM develops and tests hybrid pixel
detectors for HEP and others applications.
• We are interested to develop future detectors having very
small size of pixel with more functionalities , less matter,
new improvements :
• Using the 3-D electronic integration approach
• Using very deep submicronic technology (65nm technology…)
• Using the HVCMOS
• ….
We would like to thank you the fruitful IHEP-USTC
collaboration during these development phases
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