Transcript ECE 448 * FPGA and ASIC Design with VHDL

ECE 448
Lecture 5
FPGA Devices
& FPGA Design Flow
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
What is an FPGA?
Configurable
Logic
Blocks
Block RAMs
Block RAMs
I/O
Blocks
Block
RAMs
ECE 448 – FPGA and ASIC Design with VHDL
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Modern FPGA
RAM blocks
RAM
blocks
Multipliers
Multipliers/DSP
units
Logic
blocks
Logic
resources
(#Logic resources, #Multipliers/DSP units, #RAM_blocks)
Graphics based on The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
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Major FPGA Vendors
SRAM-based FPGAs
• Xilinx, Inc.
~ 51% of the market
• Altera Corp. ~ 34% of the market
• Lattice Semiconductor
• Atmel
~ 85%
Flash & antifuse FPGAs
• Actel Corp. (Microsemi SoC Products Group)
• Quick Logic Corp.
ECE 448 – FPGA and ASIC Design with VHDL
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Xilinx

Primary products: FPGAs and the associated CAD
software
Programmable
Logic Devices
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
ISE Alliance and Foundation
Series Design Software
Main headquarters in San Jose, CA
Fabless* Semiconductor and Software Company
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UMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996}
Seiko Epson (Japan)
TSMC (Taiwan)
Samsung (Korea)
ECE 448 – FPGA and ASIC Design with VHDL
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Xilinx FPGA Families
Technology
220 nm
180 nm
Low-cost
Spartan II,
Spartan IIE
120/150 nm
90 nm
65 nm
45 nm
40 nm
28 nm
Highperformance
Virtex
Spartan 3
Virtex II,
Virtex II Pro
Virtex 4
Virtex 5
Spartan 6
Artix 7
Virtex 6
Virtex 7
Spartan 6 FPGA Family
ECE 448 – FPGA and ASIC Design with VHDL
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CLB Structure
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
General structure of an FPGA
Programmable
interconnect
Programmable
logic blocks
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
ECE 448 – FPGA and ASIC Design with VHDL
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Xilinx Spartan 6 CLB
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Row & Column Relationship Between
CLBs & Slices
ECE 448 – FPGA and ASIC Design with VHDL
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Three Different Types of Slices
50%
ECE 448 – FPGA and ASIC Design with VHDL
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25%
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Slice X
ECE 448 – FPGA and ASIC Design with VHDL
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Xilinx Multipurpose LUT (MLUT)
16-bit
SR
32-bit SR
16
64xx11 RAM
RAM
4-input
LUT
64 x 1 ROM
(logic)
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
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4-input LUT (Look-Up Table) in the Basic
ROM Mode
x1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x1
x2
x3
x4
y
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
LUT
y
x1 x2 x3 x4
x1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
y
0
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0
• Look-Up tables
are primary
elements for
logic
implementation
• Each LUT can
implement any
function of
4 inputs
x1 x2
y
y
ECE 448 – FPGA and ASIC Design with VHDL
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6-Input LUT of Spartan 6
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Reset and Set Configurations
•
•
•
•
•
No set or reset
Synchronous set
Synchronous reset
Asynchronous set (preset)
Asynchronous reset (clear)
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MLUT as a 32-bit Shift Register (SRL32)
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Input/Output Blocks
(IOBs)
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Basic I/O Block Structure
D Q
EC
Three-State
FF Enable
Clock
SR
Three-State
Control
Set/Reset
D Q
EC
Output
FF Enable
Output Path
SR
Direct Input
FF Enable
Registered
Input
Q
D
EC
Input Path
SR
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IOB Functionality
• IOB provides interface between the
package pins and CLBs
• Each IOB can work as uni- or bi-directional
I/O
• Outputs can be forced into High Impedance
• Inputs and outputs can be registered
• advised for high-performance I/O
• Inputs can be delayed
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Clock Management
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
A simple clock tree
Clock
tree
Flip-flops
Special clock
pin and pad
Clock signal from
outside world
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
ECE 448 – FPGA and ASIC Design with VHDL
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Clock Manager
Clock signal from
outside world
Clock
Manager
etc.
Daughter clocks
used to drive
internal clock trees
or output pins
Special clock
pin and pad
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
ECE 448 – FPGA and ASIC Design with VHDL
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Jitter
1
2
3
4
Ideal clock signal
Real clock signal with jitter
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Superimposed cycles
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
ECE 448 – FPGA and ASIC Design with VHDL
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Removing Jitter
Clock signal from
outside world
with jitter
Clock
Manager
etc.
“Clean” daughter
clocks used to drive
internal clock trees
or output pins
Special clock
pin and pad
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
ECE 448 – FPGA and ASIC Design with VHDL
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Frequency Synthesis
1.0 x original clock frequency
2.0 x original clock frequency
.5 x original clock frequency
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
ECE 448 – FPGA and ASIC Design with VHDL
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Phase shifting
0o Phase shifted
90o Phase shifted
180o Phase shifted
270o Phase shifted
Figure 4-20
ECE 448 – FPGA and ASIC Design with VHDL
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
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Clock Management Tiles
DCM – Digital Clock Manager
PLL - Phase Locked Loop
ECE 448 – FPGA and ASIC Design with VHDL
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Spartan-6 Family Attributes
ECE 448 – FPGA and ASIC Design with VHDL
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Spartan-6 FPGA Family Members
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FPGA device present on the
Digilent Nexys 3 board
XC6SLX16-CSG324C
Spartan 6
family
Size
Logic
Optimized
324 pins
Package type
(Ball Chip-Scale)
Commercial
temperature range
0° C – 85° C
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FPGA Design Flow
George Mason University
FPGA Design process (1)
Design and implement a simple unit permitting to
speed up encryption with RC5-similar cipher with
fixed key set on 8031 microcontroller. Unlike in
the experiment 5, this time your unit has to be able
to perform an encryption algorithm by itself,
executing 32 rounds…..
Specification / Pseudocode
On-paper hardware design
(Block diagram & ASM chart)
VHDL description (Your Source Files)
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Functional simulation
entity RC5_core is
port(
clock, reset, encr_decr: in std_logic;
data_input: in std_logic_vector(31 downto 0);
data_output: out std_logic_vector(31 downto 0);
out_full: in std_logic;
key_input: in std_logic_vector(31 downto 0);
key_read: out std_logic;
);
end AES_core;
Synthesis
Post-synthesis simulation
FPGA Design process (2)
Implementation
Timing simulation
Configuration
On chip testing
Tools used in FPGA Design Flow
Functionally
verified
VHDL code
Design
VHDL code
Xilinx XST
Synplify Premier
Synthesis
Netlist
Xilinx ISE
Implementation
Bitstream
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Synthesis
George Mason University
Synthesis Tools
Xilinx XST
Synplify Premier
… and others
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Logic Synthesis
VHDL description
Circuit netlist
architecture MLU_DATAFLOW of MLU is
signal A1:STD_LOGIC;
signal B1:STD_LOGIC;
signal Y1:STD_LOGIC;
signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;
begin
A1<=A when (NEG_A='0') else
not A;
B1<=B when (NEG_B='0') else
not B;
Y<=Y1 when (NEG_Y='0') else
not Y1;
MUX_0<=A1 and B1;
MUX_1<=A1 or B1;
MUX_2<=A1 xor B1;
MUX_3<=A1 xnor B1;
with (L1 & L0) select
Y1<=MUX_0 when "00",
MUX_1 when "01",
MUX_2 when "10",
MUX_3 when others;
end MLU_DATAFLOW;
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Circuit netlist (RTL view)
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Mapping
LUT0
LUT4
LUT1
FF1
LUT5
LUT2
FF2
LUT3
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Xilinx XST Inputs/Outputs
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Xilinx XST Inputs
• RTL VHDL and/or Verilog files
• Constraints – XCF
Xilinx constraints file in which you can specify
synthesis, timing, and specific implementation
constraints that can be propagated to the NGC file.
• Core files
These files can be in either NGC or EDIF format.
XST does not modify cores. It uses them to inform
area and timing optimization surrounding the cores.
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Xilinx XST Outputs
• NGC
Netlist file with constraint information
• NGR
This is a schematic representation of the pre-optimized
design shown at the Register Transfer Level (RTL).
This representation is in terms of generic symbols,
such as adders, multipliers, counters, AND gates, and
OR gates, and is generated after the HDL synthesis phase
of the synthesis process.
• LOG
This report contains the results from the synthesis run,
including area and timing estimation.
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RTL view in Synplify Premier
General logic structures can be recognized in RTL view
comparator
incrementer
MUX
Crossprobing between RTL view and code
Each port, net or block can be chosen by mouse click from the
browser or directly from the RTL View
By double-clicking on the element its source code can be seen:
Reverse crossprobing is also possible: if section of code is marked,
appropriate element of RTL View is marked too:
Technology View in Synplify Pro
Technology view is a mapped RTL view. It can be seen by pressing
button
or by double-click on “.srm” file
As in case of “RTL View”, buttons
can be used here
Two additional buttons are enabled:
Pay attention:
technology view
is usually large
and presented on
number of sheets
Ports, nets and
blocks browser
- show critical path
- open timing analyst
Technology view is
presented using device
primitives
Viewing critical path
Critical path can be viewed by pressing on
Delay values are written near each component of the path
Implementation
George Mason University
Implementation
• After synthesis the entire implementation
process is performed by FPGA vendor
tools
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Implementation
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Translation
Synthesis
Circuit
Netlist
Timing
Constraints
Constraint Editor
or Text Editor
UCF
User Constraint File
Translation
NGD
Native Generic Database file
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Mapping
LUT0
LUT4
LUT1
FF1
LUT5
LUT2
FF2
LUT3
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Placing
FPGA
CLB SLICES
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Routing
FPGA
Programmable Connections
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Configuration
• Once a design is implemented, you must create a
file that the FPGA can understand
• This file is called a bit stream: a BIT file (.bit extension)
• The BIT file can be downloaded directly to the
FPGA, or can be converted into a PROM file
which stores the programming information
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Two main stages of the
FPGA Design Flow
Implementation
Synthesis
Technology
dependent
Technology
independent
RTL
Synthesis
- Code analysis
- Derivation of main logic
constructions
- Technology independent
optimization
- Creation of “RTL View”
Map
Place & Route
- Mapping of extracted logic
structures to device primitives
- Technology dependent
optimization
- Application of “synthesis
constraints”
-Netlist generation
- Creation of “Technology View”
Configure
- Placement of generated
netlist onto the device
-Choosing best interconnect
structure for the placed
design
-Application of “physical
constraints”
- Bitstream
generation
- Burning device