Transcript AutoCons - TAU Workshop

Taming the Constraints Beast:
AutoCons
Manjeri Krishnan
Brian Borchers
Texas Instruments, Inc.
1
Agenda
 Background
 AutoCons Overview
 Basic Concepts
 Some Illustrations
 Helper Scripts
 Conclusion
2
“Necessity is the Mother of Invention”
 Necessity
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Intensely manual effort of developing timing constraints
Increasing SOC complexity
Decreasing schedules and resources
Differing requirements of analysis and optimization teams
Differing requirements of chip and subchip teams
Need for speedy and error-free constraints development
Need for efficient management and maintenance of large
amounts of constraints
 Invention
 AutoCons
3
Sample Target Design
 1.2GHz, 28nm, 208mm2
 2.7B transistors, 37.7M instances
 Over 60 subchips
 Flat STA signoff at chip-level
 3 STA and OPT modes
Constraints
Beast
 Over 1500 clock definitions
 Mission mode tcl constraints
 Over 44K lines at chip-level
 Over 89K lines at subchip-level
4
Motivation for AutoCons
 Automate constraints development
 Standardize how constraints are written and developed
 Subchip to Subchip
 Subchip to Chip
 Leverage commonality among Subchips
 Distributed clock dividers, glitch-free clock muxes, etc.
 SerDes, RAMs, PM, DFT
 Extract Subchip and Chip constraints from same database
 Abstract out details of constraints development
 Share lessons learned quickly among Subchips
5
AutoCons Overview
 AutoCons = Automatic Constraints Generator
 ~8000 line Perl program
 Input = Golden Constraints INput (GCIN) file
 Input is a set of multi-dimensional hash-style Perl
variables
 Bottoms-up approach to constraints development
 Abstracted view of constraint related objects
 Subchip and Chip constraints from same Database
 Automation without giving up control
6
AutoCons Overview - Flow
SubchipA
GCIN
file(s)
miss.tcl
hold.tcl
atpg.tcl
SubchipC
SubchipC
SubchipA
miss.tcl
hold.tcl
atpg.tcl
AutoCons
SubchipB
Top
miss.tcl
tftc.tcl
atpg.tcl
22K lines
300K lines
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Basic Concepts
 Keywords for pre-determined constructs
 mclkport__, clkdivh__, clkmux__, etc.
 Clock period variables for clock associations and
groupings
 CLKn_PERIOD, TESTCLK_PERIOD, etc.
 Automatic translation to chip-level
 Instance-specific constraints replication
 General constraints
 RAM, PM, DFT, etc.
 Helper scripts
 Clock tracer
 Subchip IO constrainer
8
Sample GCIN Entries
#-- clkdivh__chip1 (from GCIN for subchip1)
#-$autocons{ ref_subchip1 }{ clkdivh__chip1 }{ hierpath } = "Ictl/i_pll_ctrl_clkdivctl_0/U_div/I_ti_ipg_divh";
$autocons{ ref_subchip1 }{ clkdivh__chip1 }{ srcpin } = $autocons{ ref_subchip1 }{ mclkport__pllclk1 }{ clkpin };
$autocons{ ref_subchip1 }{ clkdivh__chip1 }{ mastclk } = $autocons{ ref_subchip1 }{ mclkport__pllclk1 }{ clkname };
$autocons{ ref_subchip1 }{ clkdivh__chip1 }{ mastclk_top } = $autocons{ ref_chip1 }{ mclkpin__corepll }{ clkname };
$autocons{ ref_subchip1 }{ clkdivh__chip1 }{ clkname } = "gclk_pll_chip_clk1";
$autocons{ ref_subchip1 }{ clkdivh__chip1 }{ clkname_top } = "gclk_pll_chip_clk1";
$autocons{ ref_subchip1 }{ clkdivh__chip1 }{ clkperiod } = "\$CLK1_PERIOD";
$autocons{ ref_subchip1 }{ clkdivh__chip1 }{ divfact } = 1;
$autocons{ ref_subchip1 }{ clkdivh__chip1 }{ olddivh } = "true";
#-- VBUS clock (from GCIN for subchip2)
#-$autocons{ ref_subchip2 }{ clkdivh__subclk3 }{ hierpath } = "Idivh_clk3_clk";
$autocons{ ref_subchip2 }{ clkdivh__subclk3 }{ srcpin } = $autocons{ ref_subchip2 }{ mclkport__clk1clk }{ clkpin };
$autocons{ ref_subchip2 }{ clkdivh__subclk3 }{ mastclk } = $autocons{ ref_subchip2 }{ mclkport__clk1clk }{ clkname } ;
$autocons{ ref_subchip2 }{ clkdivh__subclk3 }{ mastclk_top } = $autocons{ ref_subchip1 }{ clkdivh__chip1 }{ clkname } ;
$autocons{ ref_subchip2 }{ clkdivh__subclk3 }{ clkname } = "gclk_clk3";
$autocons{ ref_subchip2 }{ clkdivh__subclk3 }{ clkperiod } = "\$CLK3_PERIOD";
$autocons{ ref_subchip2 }{ clkdivh__subclk3 }{ divfact } = "3";
$autocons{ ref_subchip2 }{ clkdivh__subclk3 }{ mode_top } = "both";
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AutoCons Abstraction
CLK_DIVH
Create Clock Definitions here
Disable Timing Arcs here
Set Multicycle Exceptions here
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Sample Instance Specification (1/2)
 Two instances of ref_subchip3:
 Imysc0
 Imysc1
 Specification in GCIN for subchip3:
$autocons{ ref_subchip3 }{ instances } = "Imysc0, Imysc1";
;#-- comma separated list of instances
;#-- (for use at chip-level)
 Clock defined at ref_subchip3 level:
 gclk_myclk1_clk
 Corresponding clocks defined at chip level:
 gclk__Imysc0__myclk1_clk
 gclk__Imysc1__myclk1_clk
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Sample Instance Specification (2/2)
 Clock definition at subchip level:
create_generated_clock [get_pins Idivh_clk3_clk/I_orgate_finalnand/clk_na2_nand_0/y] \
-name gclk_clk3 \
-source [get_ports refclk1_clk] \
-master_clock mclk_clk1 \
-edges { 1 4 7 } -edge_shift { 0 0 0 } -add
 Corresponding clock definitions at chip level:
create_generated_clock [get_pins Imysc0/Idivh_clk3_clk/I_orgate_finalnand/clk_na2_nand_0/y] \
-name gclk__Imysc0__clk3 \
-source [get_pins Imysc0/refclk1_clk] \
-master_clock gclk_pll_chip_clk1 \
-edges { 1 4 7 } -edge_shift { 0 0 0 } –add
create_generated_clock [get_pins Imysc1/Idivh_clk3_clk/I_orgate_finalnand/clk_na2_nand_0/y] \
-name gclk__Imysc1__clk3 \
-source [get_pins Imysc1/refclk1_clk] \
-master_clock gclk_pll_chip_clk1 \
-edges { 1 4 7 } -edge_shift { 0 0 0 } -add
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Helper Scripts – Clock Tracer
 Used to understand clocking of given netlist
 Traces gate-mapped netlist to identify clock objects
and clock flow
 Starts with all clock pins and traces backwards,
then forwards
 Finds all clock dividers, clock muxes, and primary clock IO
(plus tieoffs, fanout stats, and control points)
 Runs iteratively, taking in design-specific information
as needed
 Produces a textual representation of clock flow and objects
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Sample Clock Tracer Output
CLOCK BRANCH SRC: refclk1_clk
>> CLOCK TREE FANOUT = 259 <<
Idbg/Idbg_wrap/Idivh_clk3_clk/I_c_clkin_clockgate/tiboxv_clk_icg_icg_0/clkin (icg_f4_svt)
Idbg/Idbg_wrap/Idivh_clk3_clk/I_c_ti_ipg_div1_dummynand1/tiboxv_clk_na2_nand_0/a (ctnand2_f8_dh_svt)
Idbg/Idbg_wrap/Idivh_clk3_clk/I_c_ti_ipg_div1_dummynand1/tiboxv_clk_na2_nand_0/b (ctnand2_f8_dh_svt) **Logic 1**
<SNIP>
Idbg/Idbg_wrap/Idivh_clk3_clk/I_c_clksel_divideone_clockgate/tiboxv_clk_icg_inv_icg_0/clkin (icg_f4_svt)
Idbg/Idbg_wrap/Idivh_clk3_clk/I_c_ti_ipg_mx_finalnand/tiboxv_clk_na2_nand_0/a (ctnand2_f8_dh_svt)
>> CLOCK TREE FANOUT = 25188 <<
Idbg/Idbg_wrap/Idbg/I_dvs/I_ct_tbr/I_clkgen/I_sys/U0_FIRSTGCM/tiboxv_clk_icg_icg_0/clkin (icg_f4_svt)
Idbg/Idbg_wrap/Idbg/I_dvs/I_ct_tbr/I_clkgen/I_sys/U0_SECONDGCM_0/tiboxv_clk_icg_icg_0/clkin (icg_f4_svt)
Idbg/Idbg_wrap/Idbg/I_dvs/I_ct_tbr/I_tbrI_mem_ctl/I_rd_clk_mx2/tiboxv_clk_mx2_mux_0/b (ctmux2_f6_dh_svt)
>> CLOCK TREE FANOUT = 24 <<
CLOCK BRANCH SRC: Idbg/Idbg_wrap/Idivh_clk3_clk/I_c_ti_ipg_mx_finalnand/tiboxv_clk_na2_nand_0
Idbg/Idbg_wrap/Idbg/I_dvs/I_mipi_stm/U0_<snip>/Itiboxh_clk_mx2/tiboxv_clk_mx2_mux_0/b (ctmux2_f6_dh_svt)
CLOCK BRANCH SRC: Idbg/Idbg_wrap/Idivh_clk3_clk/I_c_clkin_clockgate/tiboxv_clk_icg_icg_0
Idbg/Idbg_wrap/Idivh_clk3_clk/I_c_ti_ipg_divh_clkoutreg/tiboxv_clk_reg_apncn_reg_0/clk (ctsdffbqs_f4_dh_svt)
Idbg/Idbg_wrap/Idivh_clk3_clk/I_c_ti_ipg_orgate_nanda/tiboxv_clk_na2_nand_0/a (ctnand2_f8_dh_svt)
Idbg/Idbg_wrap/Idivh_clk3_clk/I_c_ti_ipg_orgate_nanda/tiboxv_clk_na2_nand_0/b (ctnand2_f8_dh_svt) **Control Branch**
Idbg/Idbg_wrap/Idivh_clk3_clk/I_c_ti_ipg_orgate_finalnand/tiboxv_clk_na2_nand_0/b (ctnand2_f8_dh_svt)
Idbg/Idbg_wrap/Idivh_clk3_clk/I_c_clksel_divout_clockgate/tiboxv_clk_icg_inv_icg_0/clkin (icg_f4_svt)
Idbg/Idbg_wrap/Idivh_clk3_clk/I_c_ti_ipg_mx_finalnand/tiboxv_clk_na2_nand_0/b (ctnand2_f8_dh_svt)
>> CLOCK TREE FANOUT = 25188 <<
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Helper Scripts – Subchip IO Constrainer
 Used to constrain subchip IO
 Runs on gate-mapped netlist with AutoCons constraints
loaded
 Traces netlist to associate each input and output port
with correct clocks
 Applies IO constraint as a predetermined fraction of
clock cycle time
 Handles situation of an input (output) port that is
captured (driven) by multiple clocks
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IO Constraining Issue
iport
vclk1
clk1
vclk2
/2
clk2
set_input_delay vclk1_budget –clock vclk1 iport
set_input_delay vclk2_budget –clock vclk2 iport
set_false_path –from vclk1 –through iport –to clk2
set_false_path –from vclk2 –through iport –to clk1
16
Conclusion
 Automation is the way forward
 AutoCons is here to stay (4 successful SOCs so far)
 Standardization is a key enabler for automation
 Methodology changes to enable more automation
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18
Backup Slides
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STA Modes – New 3-Mode Strategy
• miss.tcl
– At-speed setup
– Covers Mission and TFT-Capture setup timing
• hold.tcl
– All hold
– Covers Mission, TFT-Capture, and ATPG hold
• atpg.tcl
– ATPG setup
– Covers ATPG shift setup
20
STA Modes – Block versus Top
Mission setup
miss.tcl
Mission hold
miss.tcl
TFT-Capt setup
hold.tcl
TFT-Capt hold
tftc.tcl
ATPG-Shft setup
atpg.tcl
ATPG-Shft hold
atpg.tcl
ATPG-Capt hold
TFT-Capt = Transition (or Delay) Fault Test Capture
21
Fully Automatic IO Constraining
• Clocking configurations that can be fully constrained automatically
eag_cpu, eag_l2_tbnk
mclk
mclk
fclk
bcp, bcr, fftc, intc, qm, tac, vcp
mclk
divh
gclk
mclk
divh
gclk
fclk
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So What’s in AutoCons Constraints?
• Clock definitions – divh, divp, clkmux, etc.
• Clock lists and Clock-to-Clock exceptions (set_clock_groups)
• Standard constants - clock periods, object attribute names
• Standard variables and collections:
– Collections: clkports, iports, oports
– Path Groups: IPATH, OPATH, FTPATH
– Default IO delay variables: default__<clkname>__io_delay
• Common timing exceptions:
– mode-related case settings
– divh, clkmux related timing exceptions
– DFT, RAM, PM related timing exceptions
• IO delay constraints where possible
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