Transcript handsets_design_Oct to customers

The World Leader in High Performance Signal Processing Solutions
Handset applications using
Low Voltage, Low Ron Switches
Agenda
 Product
Portfolio
 Handset applications
 Important
Specs for Handset Switches
 Introduction to CMOS switches
 Design Specifications
 Design Tradeoffs
 Analog Devices switches
 Package
developments
 USB Switching - optional
 Level Translators - optional
Switches for Consumer Products
1.65V – 5.5V Supply range
Ron < 1 W
Ron < 4 W
ADG801/2
3V, 5V
ADG849
Supply Range
ADG884
ADG721/2/3
ADG736
ADG788
ADG787
ADG888
ADG779
ADG701/2
1.65V – 3.6V
ADG821/2/3
ADG819
ADG741/2
ADG859
ADG841/2
1 x SPST
ADG839
1 x SPDT
ADG836
2 x SPST
Switch Configuration
2 x SPDT
4 x SPDT
Handset Applications
 Audio
Switching
 Speaker/ringer
 Internal/external
 Data
Switching
 USB
 UART
 RS232
speaker – handsfree
Handset Audio Switching
Requirements
32 ohm
For phone
 Configuration

eg 2 x SPDT
 Board

area
Tiny package
 Minimum

distortion
Ron Flatness
 Loudness

8 ohm
For ring and MP3
Very low absolute Ron (~0.5ohms)
 Minimum

signal loss
Baseband
Chip
High continuous currents
Melody/voice & hands-free
Handset Data Switching
Requirements
 Configuration
 Board

area
Tiny package
 Bandwidth

Eg USB 1.1 – 12Mbps
 Minimum

signal loss
Low absolute Ron (~2.5ohms)
 Differential
system-Channel
matching

Delta Ron
 Minimum

distortion
Ron Flatness
UART
RS232
Transceiver
USB
USB
transceiver
Digital BB
eg 2 x SPDT
Socket Connection

Important specifications in handset switches
 Package
 The
smaller the better!
 Ron
 Absolute
value needs to be low because the switch is in series
with the Speaker
 Low Ron also means lower Ron Flatness  less audio distortion
 Current
Handling Capabilities
= I2R  More current through the switch means more power,
thus louder audio
P
 Power
 Many
consumption
products are battery-operated, therefore power consumption
is critical
Basic MOSFET structure of CMOS Analog switch
 The
CMOS switch is a parallel combination of PMOS and NMOS,
Field effect transistors which operate in the non-saturated region.
 The
input buffer level shifts the digital input and applies
signal to drivers
 Drivers set the timing so that PMOS and NMOS are turned
“on” or “off”.
 NMOS on when gate is HI, PMOS on when gate is LO.
 Basic building block for multi-channel switch
driver
inverter
PMOS
Drain I/O
Source I/O
Input buffer
Digital
input
driver
NMOS
Figure 1. MOS structure of a single CMOS switch channel
Advantages of parallel structure
Ron of
NMOS only
source
drain
In
Vsource (V)
Ron (Ω)
Ron (Ω)
parallel with
outputs
 Bi-directional operation
 Relatively constant On-resistance over input signal range
 For both NMOS and PMOS to have same Ron, PMOS is more than
twice the area of NMOS
Ron (Ω)
 Rail-to-Rail
Vsource (V)
Rpmos
Vsource (V)
Rnmos
source
drain
Ron of
PMOS only
source
Digital input
drain
Ron of CMOS
Absolute On-Resistance
 Ron
varies with input signal
 Ron varies with supply
 Ron varies with temperature
Ron flatness/Audio Distortion
Flatness = Max_Ron – Min_Ron
 Translates directly into distortion through the switch
 Reduced by using back-gate switching
 Ron
1
VDD = 5V
ON RESISTANCE
0.8
Ron max
0.6
0.4
0.2
Ron min
0
0
1
2
3
Vd, Vs - V
4
5
Delta Ron - On resistance Channel
Matching
 On
resistance matching (ΔRon): Difference in Ron between
channels
 Achieved by good layout techniques
 Differential switching; ensures equal propagation delay
2.5
2.4
2.3
2.1
2
1.9
1.8
Voltage
S1A
S1B
S2A
S2B
3
6
9
2
5
3.
3.
3.
4.
4.
3
7
8
1.
2.
5
1.
4
2
1.
2.
9
0.
1
6
0.
2.
3
0.
1.7
0
Ron
2.2
Continuous current
 Need
large tracks and careful routing to handle current
 Trade-off
with package size
 Reliability
specs (current vs track width) and maximum
junction temperature of silicon determine max. continuous
current
 Excess
currents lead to electromigration over time
 Reflow of metal causing increase in Ron and eventually opens
 ADG849
 400mA
continuous current
Charge Injection
A
measure of the glitch impulse transferred from the digital input to
the analog output during switching.
 Caused by stray capacitance associated with the NMOS and PMOS
transistors
 For both NMOS and PMOS to have same Ron, PMOS is approx three
times the area of NMOS hence cap of PMOS= 3x cap of NMOS
 Balanced NMOS and PMOS => low Qinj

Achieved by adding compensations caps
Capacitance
 Mainly
dependent on switch area
 Try to minimise during layout
 Ultra-Low Ron  Very large Switch Area  Lots of
parasitic capacitance  Low bandwidth
When switch is on
input
CS
CS(on)
output
Cchannel CD
= CD(on) = CS+ CD + Cchannel
When switch is off
input
output
CS
CD
CS(off)
= CS
CD(off)
= CD
Leakage Currents
 Leakage
increase as temp
increase
 Higher voltage => higher
leakage
Source
: ADG836 data sheet
Design tradeoffs
α 1/(size of switch)
 Continuous current needs to be high
 Ron
 Both
of these specs mean you need a large switch area
 This means:
 Larger
package
 Higher parasitic capacitance – lower bandwidth
 Higher leakage
 Higher charge injections
Specification tradeoffs
 Package
Ron  Very large Switch Area (package vs Ron tradeoff)
 Large tracks for carrying the current  needs area
 Ultra-Low
 Bandwidth
Ron  Very large Switch Area  Lots of parasitic
capacitance  Low bandwidth
 Ultra-Low
 Charge
injection
capacitance  large Charge Injection
 Large Switch/track Area  no room for Qinj compensation
capacitors
 Large
ADG859: 1.3W SPDT in the smallest
standard package
KEY BENEFITS
Package: Tiny 6-pin device in 1.65 x
1.66 x 0.57mm package
 Ron: 3 W at 5V operation
 Distortion: 0.5 W

Specifications
VRANGE
RON
RON Flat
Bandwidth
Qinj
Package
Temp
1.8 V to 5.5 V
3W
0.5 W
70MHz
30pC
SOT66
-40°C – 85°C
Alternative to WLCSP
ADG888 – 0.45 W Dual DPDT Switch in
WLCSP/LFCSP/TSSOP
ADG888
S1A
D1
S1B
KEY BENEFITS
S2A
Ultra-low RON 0.45 W typ
 WLCSP and TSSOP packages
 3V, 5V operation
 400mA Continuous Current
 600mA Peak current
D2

S2B
IN1
S3A
D3
S3B
S4A
D4
S4B
IN2
Specifications
VRANGE
1.8 V to 5.5 V
RON
0.45 W
SWITCHES SHOWN FOR A LOGIC "1" INPUT
RON Flat
0.1 W
Leakage
3nA
Smallest Quad Audio Sw in the world
Qinj
Package
Temp
50pC
WLCSP;
LFCSP;
TSSOP
-40°C – 85°C
The World Leader in High Performance Signal Processing Solutions
Packaging Advances
LFCSP, WLCSP, advances in std plastic packages
Packaging Innovation compliments Product Innovation
Standard Offerings
TQFP
SSOP
TSOT
SOIC
TSSOP
SOIC-N
SOT
SOIC-W
SC70
QSOP
PDIP
LCC
Standard
package
development
Three-pronged
approach
Tiny Analog Switches
 Lowest
Ron parts
Minimum distortion
 Excellent for audio

 Handset,
PDA, Notebook
Config
Generic
Ron (W)
Supply
Package
SPDT
ADG819
0.5
1.8-5.5V
WLCSP
SPDT
ADG749
2.5
1.8-5.5V
SC70
SPDT
ADG779
2.5
1.8-5.5V
SC70
2x SPDT
SPST
ADG787
ADG741/2
2
2
1.8-5.5V
1.8-5.5V
WLCSP
SC70
2x SPDT
ADG736
4
1.8-5.5V
MSOP, CSP
2x SPDT
ADG884
0.5
1.8-5.5V
CSP, WLCSP
SPDT
ADG849
0.95
1.8-5.5V
SC70
Packaging Innovation compliments Product Innovation
standard package  SOT66
 Perfect for handset, PDA
 New
 35%
less area than SC70
 Almost half the height!
Alternative to WLCSP
Avoid manuf issues!
ADG3231
ADG3241
ADG859*
*SPDT Audio Sw
Release 2H04
Smallest 1-bit translators
Smallest audio Sw
SOT-666 Package Outline
Wafer-Level Portfolio
Smallest possible PCB footprint
ADG819
SPDT 0.5W
Audio
ADG787
2x SPDT 4W
USB1.1
ADG888
4x SPDT 0.5W
Audio
ADG808
8x SPDT 0.5W
Audio
Green: Released
Red: Planned
ADG3308
8-channel
1.2V-5.5V
Translator
ADG884
2x SPDT <1W
Audio
ADG3304
4-channel
1.2V-5.5V
Translator
Shortlist of Recommended Handset Parts
Part Number
Description
Samples
Release
1K/Price
ADG819
0.5 W CMOS 1.8 V to 5.5 V 2:1 Mux/SPDT


$0.93
ADG849
1.8 V to 5.5 V, <1W SPDT in SC70 Package


$0.94
ADG884
0.5 W CMOS Dual 2:1 Mux/SPDT in WLCSP

Oct04
TBA
ADG836
<0.8 W CMOS 1.6V to 3.6V Dual SPDT/2:1 Mux


$0.98
ADG779
CMOS 1.8 V to 5.5 V, 2.5 W SPDT in Tiny SC70


$0.64
ADG787
2 W CMOS 1.8 V to 5.5 V 2:1 Mux/SPDT USB1.1 Switch

Nov04
$0.92
ADG736
Low Voltage 2.5 W Dual SPDT Switch


$0.90
ADG3308
1.2V to 5.5V, 8-bit Bi-dir Logic Level Translator

Nov’04
$1.60
ADG3304
1.2V to 5.5V, 4-bit Bi-dir Logic Level Translator

Nov’04
$0.96
ADG3241
2.5 V/3.3 V, 1-Bit, 2-Port Level Translator Bus Switch


$0.43
ADG3242/3
2.5 V/3.3 V, 2 Bit, Level Translators


$0.56
ADG3231
Low Voltage, Single-Channel Level Translator


$0.43
The World Leader in High Performance Signal Processing Solutions
USB1.1 and USB2.0 Switching
ADG7xx Series, ADG8xx Series and ADG324x series
USB 1.1 Switch requirements
 USB

1.1 Signal levels
3.6V max signal level, 0V min spec
ADI switches are ideal for USB1.1
 All ADG7xx, most ADG8xx comply
5V supply
 Rail to rail operation
 Low power (<1uA Idd)
 Low Ron:

ADG7xx  ~3Ω
 ADG8xx  <1Ω
 Excellent flatness characteristic

 ADI
Advantage
Low Ron minimizes signal loss
 Flat Ron reduces signal distortion

USB 1.1 Switch requirements (continued)
 Bandwidth
 USB1.1
 Again
> 12MHz required
is 12Mbps signal
ADG7xx ideal
 Suitable
configurations
 Suitable bandwidth (majority
>200MHz)
Source: ADG736
Bandwidth 200MHz
ADI guarantee compliance to the USB
standard
Eg.  ADG736 USB 1.1 eye diagram.


Input = random, 3V, 12Mbps differential
signal
Excellent ‘open eye’ characteristic
What makes a good eye diagram?
Eye characteristic
Switch spec
No loss
Low Ron
Open eye, good edge
integrity
High B/W, good
flatness.
Low jitter
Linear with time.
Equal propagation
delays
Channel to channel
symmetry.
New USB1.1 Compatible part: ADG787 Dual
SPDT Switch
(Break-Before-Make)
ADG787
S1A
KEY BENEFITS
D1
S1B
Bandwidth: 150MHz
 WLCSP, LFCSP & µSOIC packages
 2 W Ron
 Flatness 0.4 W

IN1
IN2
S2A
D2
S2B
Specifications
VRANGE
1.8 V to 5.5 V
Schedule
Released
RON
2W
RON Flat
0.4 W
Bandwidth
150MHz
Qinj
Package
Temp
30pC
WLCSP;
LFCSP
µSOIC
-40°C – 85°C
ADG787: Ron vs Supply for the 4 channels,
Vdd = 4.5V
2.5
2.4
2.3
Ron
2.2
2.1
2
1.9
1.8
1.7
0
0.
3
0.
6
0.
9
1.
2
1.
5
1.
8
2.
1
2.
4
2.
7
3
Voltage
S1A
S1B
Note: Channel matching very good
S2A
S2B
3.
3
3.
6
3.
9
4.
2
4.
5
USB 1.1 Selection Table
Package
Spec’s
5V
16ld TSSOP/SOIC
2Ω Ron, >200MHz B/W
Quad SPST
5V
20ld CSP
2Ω Ron, >200MHz B/W
ADG721/2
Dual SPST
5V
8ld uSOIC
2Ω Ron, >200MHz B/W
ADG736
Dual SPDT
5V
10ld uSOIC
2Ω Ron, >200MHz B/W
ADG774
Quad SPDT
5V
16ld SOIC
2Ω Ron, >200MHz B/W
ADG784
Quad SPDT
5V
20ld CSP
2Ω Ron, >200MHz B/W
ADG788
Quad SPDT
5V
20ld CSP
2Ω Ron, >200MHz B/W
ADG787
Dual SPDT
5V
10ld MSOP
WLCSP
2Ω Ron, 150MHz B/W
ADG821/2
Dual SPST
5V
8ld uSOIC
<1Ω Ron, 24MHz B/W
ADG836
Dual SPDT
3.6V
12ld LFCSP/10ld
uSOIC
<1Ω Ron, 57MHz B/W
ADG709
Dual 4:1 Mux
5V
16ld TSSOP
3Ω Ron, 100MHz B/W
ADG729
Dual 4:1 Mux
5V
16ld TSSOP
I²C, 3Ω Ron, 100MHz B/W
ADG739
Dual 4:1 Mux
5V
16ld TSSOP
SPI, 3Ω Ron, 100MHz B/W
ADG759
Dual 4:1 Mux
5V
20ld CSP
3Ω Ron, 100MHz B/W
Generic
Config.
Supply
ADG711/2/3
Quad SPST
ADG781/2/3
USB1.1
USB 2.0 Switch requirements
 USB2.0
signal levels:
 +/-400mV
diff signal
 Bandwidth
 Random
 Low
Requirements:
480Mbps
Absolute Ron and Flatness
 Similar
requirements to USB1.1
 Backward
 Majority
Compatibility
of systems need to be
backward compatible with USB1.1
Source: ADG774A / ADG3257
Bandwidth: 410MHz
Comparisons of eye diagrams
Input
= random, 400mV, 480Mbps differential signal
ADG3257 (BW = 410 MHz)
ADG736 (BW = 200MHz)
USB 2.0 & Universal USB Selection Table
Generic
Config.
Supply
AG3241
SPST
ADG3242
USB2.0
Package
Specifications
3.3V
SC70, SOT66
2Ω Ron, >480MHz B/W
2x SPST
3.3V
SOT23
2Ω Ron, >480MHz B/W
ADG3243
2x SPST
3.3V
SOT23
2Ω Ron, >480MHz B/W
ADG3245
8x SPST
3.3V
TSSOP, LFCSP
2Ω Ron, >480MHz B/W
ADG3246
10x SPST
3.3V
TSSOP, LFCSP
2Ω Ron, >480MHz B/W
ADG3247
16x SPST
3.3V
TSSOP, LFCSP
2Ω Ron, >480MHz B/W
ADG3248
SPDT
3.3V
SC70
2Ω Ron, >480MHz B/W
ADG3249
SPDT
3.3V
SOT23
<1Ω Ron, >480MHz B/W
Generic
Config
Supply
Package
Specifications
ADG774A
4x SPDT
5V
QSOP
2.2Ω Ron, >400MHz B/W
ADG3257
4x SPDT
5V
QSOP
2.2Ω Ron, >400MHz B/W
Univ
The World Leader in High Performance Signal Processing Solutions
Digital Switches/Level
Translators
Std translators, Wide range translators, Fully bidirectional translators
What’s driving the need for translators?
 Digital
voltage migration following Moore’s Law to 90nm and below
Faster operation, lower power
 90nm requires 1.2V supply
 45nm in pipeline
 Expect no i/o due to COST

 Analog

Aim at first generation
2nd gen will be integrated
ICs, legacy ICs at 2.5V and higher, in general
Performance reasons, S/N ratio
 Need
to communicate between ICs!
Translators adjust
CMOS/TTL for zero
bit loss
High
+3.3 V BUS
“Oops
parts”
+2.5 V BUS
VOH MIN
High
VIH MIN
+3.3 V
LOGIC
+2.5 V
LOGIC
VIL MAX
Low
VOL MAX
Low
0V
Level Translation
Switch
0V
ADG3241 – 3.3 V/2.5 V 1-Bit, Level Translator
Digital Switch Portfolio (Low-Bit)
KEY BENEFITS

Selectable Level Translation


Allow direct 3.3 V to 1.8 V translation
 No need for discrete components
High Performance In Small Size



Data Rate 1.5 Gbps
 Very low 225ps propagation delay
Uni-directional Level Translation, Bi-directional
signal path
Tiny SC70 package
Prop Delay
Package
Temp
Data Rate
Level Trans
Data Trans
RON
Price @ 1k
225ps
6-lead SC70
-40°C – +85°C
1.5 Gb/s
Uni-dir
Bi-dir
4.5 W
$ 0.43
ADG3242/3
 SOT23
 ADG3242 is common enable
 ADG3243 is individual enable
ADG3248
 Space-saving SC70 option
 2:1 Mux/de-mux configuration
 Std level translation* only
*Std level translation is 3.3V/2.5V or 2.5V to 1.8V translation Exception is 3.3V  1.8V translation
ADG3249
 SOT23
 2:1 Mux/de-mux configuration
 Allows 3.3 V/1.8 V translation
ADG3245 – 3.3 V/2.5 V 8-Bit, Level Translator
Digital Switch Portfolio (High-Bit)
KEY BENEFITS

Selectable Level Translation


Allow direct 3.3 V to 1.8 V translation
 No need for discrete components
High Performance In Small Size



Data Rate 1.244 Gbps
 Very low 225ps propagation delay
Uni-directional Level Translation, Bi-directional
signal path
TSSOP and LFCSP packages
Prop Delay
Package
Temp
Data Rate
Level Trans
Data Trans
RON
Price @ 1k
225ps
TSSOP, CSP
-40°C – +85°C
1.244 Gb/s
Uni-dir
Bi-dir 
4.5 W
$ 0.71
ADG3246
 10-Bit version
 Exception
is 3.3V  1.8V translation
ADG3247
 16-Bit version
Level Translators
Key Features
 Wide

range voltage translation
1.6 V to 3.6 V Supply
 UP/DOWN
Level Translation, Uni-Directional Signal Path
 Low Current Consumption <5mA
 Tiny packages:
ADG3231 in 6-SOT23 and ADG3232 in 8-SOT23
 New option… ADG3231 in SOT666 (SC89)… 40% smaller than SC70!

Vcc1 Vcc2
In
Out
ADG3231
Vcc1
Vcc2
(3.6V)
(1.6V)
In1
In2
Out
EN
ADG3232
ADG330X Family- Summary Table
Part
Number
Size
(bits)
EN Logic A I/O state
(EN=0)
Level
ADG3308
8
VCCY
Tri-stated
Tri-stated
20 Lead TSSOP
20 Lead LFCSP
20 bump WLCSP*
ADG3304
4
VCCA/VCCY
Tri-stated
Tri-stated
14 lead TSSOP
20 lead LFCSP
12 bump WLCSP*
ADG3301
1
VCCA/VCCY
Tri-stated
Tri-stated
6 lead SC70
ADG3300**
8
VCCA/VCCY
6K pull-down
Tri-stated
20 lead TSSOP,
20 bump WLCSP*
*Under development
**Pin to pin compatible with MAX3000/1/2/3
Y I/O
state
(EN=0)
Package
ADG3308 Bidirectional Level Translator
8
– Channels.
 Wide
 Low
 All
 EN
1.15 to 5.5V supply range.
quiescent current (<5mA).
I/O pins are tri-stated (EN=Low).
pin accepts only VCCY compatible levels.
 Data
rate >25Mbps
 Packages:
20 lead TSSOP
 20lead 4x4mm body LFCSP
 20 bump WLCSP (under development)

VCCA
VCCY
A1
Y1
A2
Y2
A3
Y3
A4
Y4
A5
Y5
A6
Y6
A7
Y7
A8
Y8
EN
GND
ADG3304 Bidirectional Level Translator
4
VCCA
– Channels.
 Wide
 Low
 All
1.15 to 5.5V supply range.
A1
Y1
A2
Y2
A3
Y3
A4
Y4
quiescent current (<5mA).
I/O pins are tri-stated (EN=Low).
EN
GND
 EN
pin accepts both VCCY/VCCA compatible levels.
 Data
rate >25Mbps
 Packages:
14 lead TSSOP
 20lead 4x4mm body LFCSP
 12 bump WLCSP (under development)

VCCY
ADG3301 Bidirectional Level Translator
1
– Channel.
 Wide
VCCA
VCCY
1.15 to 5.5V supply range.
Y
A
 Low
 All
quiescent current (<5mA).
I/O pins are tri-stated (EN=Low).
 EN
GND
pin accepts both VCCY/VCCA compatible levels.
 Data
rate >25Mbps
 Packages:
6
EN
lead SC70
ADG3300 Bidirectional Level Translator
8

– Channels
VCCA
second source for MAX3000/1/2/3.
 Wide
 Low
1.15 to 5.5V supply range.
quiescent current (<5mA).
 EN
pin accepts VCCY/VCCA compatible
levels.
 Data
rate >25Mbps
VCCY
A1
Y1
A2
Y2
A3
Y3
A4
Y4
A5
Y5
A6
Y6
A7
Y7
A8
Y8
EN
 Packages:
20 lead TSSOP
 20 bump WLCSP (under development)

GND
ADG330X Family- Applications
Memory Address & Data Bus Level Translation
ADG3300/8
Data bus
A I/O
Y I/O
mP
Address bus
Memory
A I/O
Y I/O
ADG3300/8
ADG330X Family- Applications
Level translation For Dual Full Duplex Serial Port
100nF
100nF
1.8V
3.3V
VCCA
Microprocessor
/Microcontroller
/DSP
GND
VCCY
Y1
RX1
Y2
TX1
A3
Y3
RX2
A4
Y4
TX2
EN
GND
GND
TX1
A1
RX1
A2
TX2
RX2
ADG3304
Microprocessor
/Microcontroller
/DSP
Designing with ADG330X Level translators
 General
 Supply
requirements for Level translators:
voltage range
 Speed
 Driving
requirements
 Loading
requirements
Designing with ADG330X Level translators
Supply voltage range:

VCCA: 1.15V to 5.5V

VCCY: VCCA to 5.5V

IMPORTANT: VCCA ≤ VCCY !
Designing with ADG330X Level translators
Guaranteed Data rate
VCCY
1.8V
(1.65V to 1.95V)
2.5V
(2.3V to 2.7V)
3.3V
(3.0V to 3.6V)
5V
(4.5V to 5.5V)
1.2V
(1.15V to 1.3V)
25Mbps
30Mbps
40Mbps
40Mbps
1.8V
(1.65V to 1.95V)
-
45Mbps
50Mbps
50Mbps
2.5V
(2.3V to 2.7V)
-
-
60Mbps
50Mbps
3.3V
(3.0V to 3.6V)
-
-
-
50Mbps
5V
(4.5V to 5.5V)
-
-
-
-
VCCA
* Represents the minimum guaranteed data rate for the given loading
conditions in both A-Y and Y-A directions.
Load capacitance: 50pF for A to Y direction, 15pF for Y to A direction.
Selection Guide Available
(www.switch-mux.com)
Updated every 6 months!