Transcript RISC Machine by Kim Le

RISC MACHINE
By: Kim Le
What is RISC?
 Reduced Instruction Set Computer. is a type of microprocessor architecture that
utilizes a small, highly-optimized set of instructions, rather than a more specialized
set of instructions often found in other types of architectures.
Brief History
 The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s
and early 80s
 The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed with a
similar philosophy which has become known as RISC
 one cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle.
This is due to the optimization of each instruction on the CPU and a technique called ;
 pipelining: a techique that allows for simultaneous execution of parts, or stages, of
instructions to more efficiently process instructions;
 large number of registers: the RISC design philosophy generally incorporates a larger
number of registers to prevent in large amounts of interactions with memory
Pipelining
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fetch instructions from memory
read registers and decode the instruction
execute the instruction or calculate an address
access an operand in data memory
write the result into a register
Problem with Pipelining?
 RISC processors operate at more than one cycle per instruction. The processor might
occasionally stall a a result of data dependencies and branch instructions.
The advantages of RISC
 Speed. Since a simplified instruction set allows for a pipelined,
superscalar design RISC processors often achieve 2 to 4 times the
performance of CISC processors using comparable semiconductor
technology and the same clock rates.
 Simpler hardware. Because the instruction set of a RISC processor
is so simple, it uses up much less chip space; extra functions, such
as memory management units or floating point arithmetic units, can
also be placed on the same chip. Smaller chips allow a
semiconductors manufacturer to place more parts on a single silicon
wafer, which can lower the per-chip cost dramatically.
 Shorter design cycle. Since RISC processors are simpler than
corresponding CISC processors, they can be designed more quickly,
and can take advantage of other technological developments sooner
than corresponding CISC designs, leading to greater leaps in
performance between generations.
The hazards of RISC
 Code Quality
 The performance of a RISC processor depends greatly on the code that it is
executing. If the programmer (or compiler) does a poor job of instruction
scheduling, the processor can spend quite a bit of time stalling: waiting for the
result of one instruction before it can proceed with a subsequent instruction.
Debugging
 If scheduling (and other optimizations) are turned off, the machine-language
instructions show a clear connection with their corresponding lines of source.
However, once instruction scheduling is turned on, the machine language instructions
for one line of source may appear in the middle of the instructions for another line of
source code.
RISC Vs. CISC
 CISC
 Emphasis on hardware
 Includes multi-clock
complex instructions
 Memory-to-memory:
"LOAD" and "STORE"
incorporated in
instructions
 Small code sizes,
high cycles per second
Transistors used for
storing
complex instructions
 RISC
 Emphasis on software
 Single-clock,
reduced instruction only
 Register to register:
"LOAD" and "STORE"
are independent
instructions
 Low cycles per second,
large code sizes
 Spends more transistors
on memory registers
CISC and RISC Convergence
 Simultaneous Multi-Threading
 Simultaneous Multi-Threading (SMT) allows multiple threads to
be executed at the exact same time. Threads are series of tasks
which are executed alternately by the processor.
 Value Prediction
 Value prediction is the prediction of the value that a particular
load instruction will produce. Load values are generally not
random, and approximately half of the load instructions in a
program will fetch the same value as they did in a previous
execution.
Where RISC is use?
Graphic Work Station
Apple
PA-RISC HP Work station
Intel Strong ARM processor (Mobile CPU)
IBM (Work Station)
MOTOROLA (Hand Held Device)
WHY RISC IS FALLING?
 Require large amount of cache memory $$$$$$
 Many companies were unwilling to take a chance with the emerging
RISC technology. Without commercial interest, processor
developers were unable to manufacture RISC chips in large enough
volumes to make their price competitive.
 Software Compatibility issues
 Too Hard to Debug
Bibliography
http://physinfo.ulb.ac.be/divers_html/Powe
rPC_Programming_Info/intro_to_risc/irt5_r
isc2.html
http://cse.stanford.edu/class/sophomorecollege/projects-00/risc/