Transcript An 81MHz, 1280 x 720pixels x 30frames/s MPEG

Class Presentation of
Custom DSP Implementation Course on:
ECE Department – University of Tehran
The Newest DSP Chips
Introduced in ISSCC 2005
Presented by:
Behzad Eghbalkhah
May 2005
This is a class presentation. All data are copy rights of their
respective authors as listed in the references and have been
used here for educational purpose only.
Outline

First Generation CELL Processor
 A 2-Core Multi-Threaded Itanium®-Family
Processor
 4th-Generation 1.8GHz Dual-Core SPARC V9
Microprocessor
 An 81MHz 1280×720 Pixels × 30frames/s
MPEG-4 Video/Audio Codec Processor
 ….
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CELL Processor
IBM
SONY
TOSHIBA
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CELL Processor (Features)
 Implemented in 90nm SOI Technology
 Including 234M Transistors for 17 physical entities
 Including 580K Repeaters and 1.4M Nets
 Including 8 layers of copper interconnect and 1 local interconnect layer
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CELL Processor (Features)
 The CELL processor is consist of
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A 64 bit Power Processor Element
(PPE) and its L2 cache
Multiple synergistic processor
elements (SPE) that each has its local
memory
A high-bandwidth internal element
interconnect bus (EIB)
2 Configurable non-coherent I/O
interfaces
A memory interface controller (MIC)
A pervasive unit that supports
extensive test, monitoring and debug
functions
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CELL Processor (performance and thermal characteristics)
The SoC presented new challenges in
thermal design of chip
The processor contains a linear sensor
and 10 digital local sensors
The chip contains 3 distinct clock
distribution systems
Prototype chip has worked in 4GHz
Worst case clock skew is less than 12psec
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CELL Processor (Used for MPEG-2 decoding)
Toshiba demonstrated that the CELL
processor can simultaneously decode
48 SDTV format MPEG-2 streams.
Of the eight synergistic processor
elements (SPE) used in the Cell, six
are used for decoding 48 MPEG-2
streams and one is used for scaling
the screen. The remaining SPE can
be used for a completely different
processing function.
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2-Core Multi-Threaded Itanium®-Family Processor
Montecito
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2-Core Multi-Threaded Itanium®-Family Processor
Features
 The processor has two dual-threaded cores integrated on die with
26.5MB of cache
 The processor is implemented in 90nm process with 7 layers of copper
interconnect
 The die is 21.5mm by 27.7mm and includes 1.72B transistors !
 With both cores at full frequency, it consumes 100W
 Improvements include the integration of 2 cores on-die, each with a
dedicated 12MB 3rd-level cache, a 1MB 2nd-level cache and dualthreading
 Power reduction is targeted as a primary design priority, so power
efficiency improved through low-power techniques and active power
management.
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2-Core Multi-Threaded Itanium®-Family Processor
 An ammeter & a microcontroller
are integrated in the chip to enable
the processor to flexibly manage the
voltage of the chip in response to
changing power consumption and
thermal conditions
 The core design has adaptive
frequency to continuously varying
voltage which in turn requires several
capabilities:
 An asynchronous interface between cores and system bus
 Frequency synthesizer that is repeatable (manufacturing / test needs)
by being as digital as possible, has a very low frequency-change
latency (1 cycle) for adapting to voltage transients
a core that robustly operates across a broad range of frequencies and
voltages.
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4th-Generation Dual-Core SPARC V9 Microprocessor
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4th-Generation Dual-Core SPARC V9 Microprocessor
Features
 This fourth-generation 64b SPARC V9 architecture processor
combines two enhanced third-generation cores into a single chip
 The chip is implemented using an advanced 90nm dual-Vt dual-gateoxide technology
 The chip contains 295 million transistors on a 336mm2 die
 operates at 1.8GHz while dissipating <100W of power at 1.1V
 Full-chip integration is accomplished using fully shielded interconnect
 Modulated Body-Biasing of devices is used as a leakage reduction
technique
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4th-Generation Dual-Core SPARC V9 Microprocessor
Characteristics
 For dynamic power reduction, the clock is gated where appropriate
to shut down inactive blocks.
 To reduce static leakage, which contributes a little over 10% to overall
power dissipation, the deployment of low-Vt transistors is limited to
less than 5% of transistor area.
 Another leakage reduction measure involves modulating the body bias
of the devices to raise the threshold voltage. Measured results show a
30% to 40% reduction in subthreshold leakage current when body bias
is applied to the transistors in the static mode.
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MPEG-4 Video/Audio Codec Processor
An 81MHz, 1280 x 720pixels x 30frames/s
MPEG-4 Video/Audio Codec Processor
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MPEG-4 Video/Audio Codec Processor
Chip Characteristics
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MPEG-4 Video/Audio Codec Processor
 Encoding of an image of 1280 × 720
pixels × 30 frames/s (720P) is achieved at
81MHz while encoding of an image of
640 × 480 pixels × 30 frames/s (VGA)
requires only 27MHz.
 The lower operating frequency of this
MPEG-4 video codec than previously
reported codecs contributes to lower
power consumption
 The MPEG-4 video codec engine consumes 43mW for encoding of
VGA/30frames/s at 27MHz and 1.3V, and 120mW for encoding of
1280 × 720 pixels × 30frames/s (720P) at 81MHz and 1.3V. The total chip
consumption is 480mW at 81MHz and 1.3V supply when a 720P image is
processed
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References
[1] D. Pham, S. Asano, M. Bolliger, M. N. Day, H. P. Hofstee,C. Johns, J. ahle, A.
Kameyama, J. Keaty, Y. Masubuchi,M. Riley, D. Shippy, D. tasiak, M. Suzuoki, M.
Wang,J. Warnock, S. Weitzel, D. Wendel, T. Yamazaki, K. azawa, “The Design and
Implementation of a First-Generation CELL Processor,” ISSCC 2005.
[2] Samuel Naffziger, Blaine Stackhouse, Tom Grutkowski, ” The implementation of a
2-core Multi-Threaded Itanium®-Family Processor,” ISSCC 2005.
[3] Jason Hart, Swee Yew Choe, Lik Cheng, Chipai Chou, Anand Dixit,Kenneth Ho,
Jesse Hsu, Kyung Lee, John Wu, “Implementation of a 4th-Generation 1.8GHz
Dual-Core SPARC V9 Microprocessor,” ISSCC 2005.
[4] Hideki Yamauchi, Shigeyuki Okada, Tsuyoshi Watanabe,Yoshihiro Matsuo,
Mitsuru Suzuki, Yasuo Ishii, Tsugio Mori,Yoshifumi Matsushita, “An 81MHz,
1280 x 720pixels x 30frames/s MPEG-4 Video/Audio Codec Processor,” ISSCC
2005.
[5] S. Torii, S. Suzuki, H. Tomonaga, T. Tokue, J. Sakai, N. Suzuki,K. Murakami, T.
Hiraga, K. Shigemoto, Y. Tatebe, E. Ohbuchi,N. Kayama, M. Edahiro, T. Kusano,
N. Nishi, “A 600MIPS 120mW 70μA LeakageTriple-CPU Mobile Application
Processor Chip,” ISSCC 2005.
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