Transcript 2102-282 Digital Electronics - IC Design & Application Research Lab.

Chapter 2
MOS Transistor Theory
Boonchuay Supmonchai
Integrated Design Application Research (IDAR) Laboratory
June 16th, 2004; Revised June 16th, 2005
B.Supmonchai
Goal of this chapter

Present intuitive understanding of device
operation

Introduction of device basic equations

Introduction of models for manual analysis
 First-Order Model

Analysis of secondary and deep-sub-micron
effects

Future trends
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The Diode
B
A
Al
SiO2
p
n
Cross-section of pn-junction in an IC process
A
A
Al
p
n
B
diode symbol
B
One-dimensional
representation
Mostly occurring as parasitic element in Digital ICs
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Diode - Depletion Region
hole diffusion
electron diffusion
p
(a) Current flow.
n
hole drift
electron drift
Charge
Density

+
x
Distance
-
Electrical
Field
(b) Charge density.

x
(c) Electric field.
x
(d) Electrostatic
potential.
V
Potential
-W 1
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
W2
MOS Transistor Theory
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Diode - Zero Bias

Build-in (Electrostatic) Potential:
N A N D 
 0  T ln  2 
 n i 
T = Thermal Voltage = kt/q = 26 mV at 300 K (Si)
ni =Intrinsic carrier concentration ~ 1.5 x 1010 cm-3
NA = Acceptor concentration (atoms/cm3)
ND = Donor concentration (atoms/cm3)
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Diode - Forward Bias
current
Excess Carriers
Excess Carriers
Diffusion
Diffusion
Typically avoided in Digital ICs
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Diode - Reverse Bias
current
Diffusion
Diffusion
The Dominant Operation Mode
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Diode Types
0.37pn0
Linear Approximation
Exponentially Distributed
Short-Base Diode is the standard in semiconductor devices
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Diode Current
VD = Diode Bias Voltage, ID = Diode Current
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Models for Diode Manual Analysis
+
VD
ID = IS(eVIDD/=T I–S(e
1)V D/T – 1)
+
–
+
+
VD
–
VD
VD
–
–
Ideal
Diode
(a) Ideal diode
model
(a) Ideal
diode Model
model
ID
+
–
ID
+
VDon
VDon
–
(typ. 0.7 V)
First-order
(b) First-order
diodeModel
model
(b)Diode
First-order
diode mode
ID  IS e
VD  T
1
Is = Saturation Current ~ 10-17 A/m2
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Example: A Diode Circuit
1: ID = IS [exp(VD /T) - 1]
2: ID = (VS - VD)/RS
Graphic Solution
ID = 0.224 mA
VD= 0.757 V
Using VD(ON) = 0.7 V
ID = 0.23 mA
VD= 0.7 V
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Diode - Junction Capacitance
Cj 
C j0
1 VD 0 
m
Cj0 = Zero-Biased Junction Capacitance
= f(physical parameters)

m = Grading Coefficient (0.5 - Abrupt, 0.33 - linear )
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Diode - Diffusion Capacitance
dQD
dID  T ID
Cd 
 T

dVD
dVD
T
 = mean transit time
= average time for a carrier to be transported
 from the junction to the metallic contact
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Diode Switching Time
R src
V1
V2
ID
V src
t= 0
VD
t= T
VD
Excess charge
Space charge
ON
OFF
ON
Switching Time is
strongly determined by
how fast the charge can
be moved around
Time
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Diode - Secondary Effects I
Avalanche Breakdown
Ecrit = 2x105 V/cm
-20
Breakdown Voltage
At Critical Field Ecrit, carriers crossing the depletion region is
accelerated to high velocity such that when they collide with
immobile silicon atoms, electron-hole pairs are created
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Diode - Secondary Effects II
Temperature Effects
IS = f(T)
T  T
Theory: 2X every 5ºC
Experiment: 2X every 8ºC
ID increases 6% per ºC
(2X every 12 º C)
(For fixed ID) VD decreases 2mV per ºC
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Diode SPICE Model
+
Neutral
Regions
RS
ID
VD
+
VD
-
ID
CD
-
ID  IS e
VD n T
1
Cj 
C j0
1 VD 0 
m
 T IS V

e
T
D
n T
n = emission coefficient (≥ 1)
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SPICE Diode Model Parameters
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What is a MOS(FET) Transistor?

Metal-Oxide-Semiconductor Field-Effect
Transistor (MOSFET, or MOS, for short)

A Four-terminal device
 Gate controls how much current can flow from the
Source to the Drain.
 Body modulates device characteristics and
parameters - secondary effect.

A switch!
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MOS Transistors - Types and Symbols
D
G
D
B
G
S
S
NMOS with Bulk Contact
NMOS Enhancement
D
D
G
G
S
S
NMOS Depletion
PMOS Enhancement
The Body terminal, if not shown, is assumed to be connected to
the appropriate supply.
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Switch Model of NMOS Transistor
Gate
| VGS |
Source
(of carriers)
Drain
(of carriers)
Open (off) (Gate = ‘0’)
Closed (on) (Gate = ‘1’)
Ron
| VGS | > | VT |
| VGS | < | VT |
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Switch Model of PMOS Transistor
Gate
| VGS |
Source
(of carriers)
Drain
(of carriers)
Open (off) (Gate = ‘0’)
Closed (on) (Gate = ‘1’)
Ron
| VGS | > | VDD – | VT | |
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| VGS | < | VDD – |VT| |
MOS Transistor Theory
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Why MOS Transistor?



MOS performs well as a switch with very few
parasitic effects.
Relatively “Simple” manufacturing process
(compared to other types of transistor)
High Integration Density
 Large and Complex circuits can be created
economically.
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The NMOS Transistor
Polysilicon
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Aluminum
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The NMOS Transistor Cross Section
Polysilicon
W
Gate
Source
n+
L
p substrate
Gate oxide
Drain
n+
Field-Oxide
(SiO2)
p+ stopper
Bulk (Body)
• n areas have been doped with donor ions (arsenic) of
concentration ND - electrons are the majority carriers
• p areas have been doped with acceptor ions (boron) of
concentration NA - holes are the majority carriers
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MOS Transistors - Behaviors

Static Behavior:
 Threshold Voltage
 Channel-Length Modulation
 Velocity Saturation
 Sub-threshold Conduction

Dynamic (Transient) Behavior:
 MOS Structure Capacitances
 Channel Capacitances
 Junction Capacitances
 Sources-Drain Parasitic Resistance
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Threshold Voltage Concept
VGS
G
+
D
S
n+
n+
n channel
p substrate
depletion
region
B
The value of VGS where strong inversion occurs is called
the threshold voltage, VT
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Threshold Voltage Components I


Work function difference between the gate and
the channel, GC
• GC = F(substrate) - M
for metal gate
• GC = F(substrate) - F(gate)
for polysilicon gate
Gate voltage component to change (invert) the
surface potential, 2F
• Fermi Potential, F = T ln(NA / ni)
• F ~ -0.3 V for p-type silicon substrate
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Threshold Voltage Components II

Gate voltage component to offset the depletion
region charge, QB / Cox
• Gate Oxide Capacitance per unit area, Cox = ox / tox
• Depletion region charge,
QB  2qN Asi  2F VSB

Voltage component to offset fixed charges in the
gate oxide
and in the silicon-oxide surface, QS / Cox


Threshold adjustment by applying the ion implantation into the channel, QI / Cox
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
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The Threshold Voltage
VT   GC  2 F 

VT  VT 0   
VT 0  VT
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V SB  0
Q B QS
Q

 I
Cox Cox Cox
 2

F
 VSB  2 F
2q  N A si
Cox
MOS Transistor Theory

Body-effect
coefficient
30
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The Body Effect - Empirically
0.9

VSB normally positive for
n-channel devices with
the body tied to ground

A negative bias causes
VT to increase from 0.45V
to 0.85V
0.85
0.8
0.75
0.7
0.65
0.6
0.55
0.5
0.45
0.4
-2.5
-2
-1.5
-1
-0.5
0
VSB (V)
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Transistor in Resistive (Linear) Mode
Assume VGS > VT
VGS
S
VDS
G
D
n+
n+
ID
n+
- V(x) +
x
B
The current is a linear function of both VGS and VDS
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Transistor in Saturation
Assume VGS > VT
VGS
S
VDS > VGS - VT
G
D
n+
n+
- VGS-VT +
x
B
Pinch-off
The current remains constant (saturates).
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I-V Relations: Long-Channel Device
Quadratic
Relationship
Linear
Relationship
Effective Length of the conductive channel is
inversely proportional to VDS
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Long-Channel I-V Plot (NMOS)
6 X 10
-4
VGS = 2.5V
VDS = VGS - VT
5
4
VGS = 2.0V
3
Linear
Saturation
2
VGS = 1.5V
1
VGS = 1.0V
0
cut-off
0
0.5
1
1.5
2
2.5
VDS (V)
NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
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Velocity Saturation
 n (m/s)
 n

  1   c

  sat
for    c
for    c
sat = 105
Constant velocity
Constant mobility (slope = µ)
c = 1.5
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 (V/µm)
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Short-Channel Devices
ID
Long-channel device
VGS = VDD
Short-channel device
Extended
saturation
V DSAT
VGS - V T
VDS
For an NMOS device with L of .25m, only a couple of volts
between S and D are needed to reach velocity saturation
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I-V Relation: Short-Channel Devices

Linear Region: VDS  VGS – VT
ID = (VDS) k’n W/L [(VGS – VT)VDS – VDS2/2]
where (V) = 1/(1 + (V/cL)) is a measure of the degree
of velocity saturation

Saturation Mode: VDS = VDSAT  VGS – VT
IDSAT = (VDSAT) k’n W/L [(VGS – VT)VDSAT – VDSAT2/2]
where VDSAT = (VGS – VT )(VGS – VT)
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Short-Channel IV Plots (NMOS)
2.5 X 10
-4
Early Velocity
Saturation
VGS = 2.5V
2
VGS = 2.0V
1.5
Linear
1
VGS = 1.5V
Saturation
VGS = 1.0V
0.5
0
0
0.5
1
1.5
2
2.5
VDS (V)
NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
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Velocity Saturation Effects
ID-VGS Characteristics

Short-Channel Devices
tend to operate in
saturation conditions
more often than the longchannel devices.

Velocity-saturation
causes the short-channel
device to saturate at
substantially smaller
values of VDS resulting in
a substantial drop in
current drive
X 10-4
6
5
4
3
2
1
0
0
0.5
1
1.5
VGS (V)
(for VDS = 2.5V, W/L = 1.5)
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2.5
MOS Transistor Theory
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A PMOS Transistor
-4
0
x 10
VGS = -1.0V
-0.2
VGS = -1.5V
I D (A)
-0.4
-0.6
VGS = -2.0V
-0.8 V = -2.5V
GS
-1
-2.5
-2
Assume all voltage
Variables negative!
-1.5
-1
-0.5
0
VDS(V)
PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = -2.5V, VT = -0.4V
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Sub-Threshold Conduction
102
ln(I
) (A)
IDD(A)
104
Linear region
8
10
1010
10120.0
kT 
S  n ln 10
 q 
Quadratic region
106
S
90 mv/decade
Subthreshold exponential region
VT
1.0
2.0

3.0
VGS (V)
Charges are “leaking” through the devices, of which the rate is
determined by the slope factor S in the subthreshold region
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A Unified Model for Manual analysis
G
S
For NMOS, all five parameters
(VTO, , VDSAT, k’, ) are positive.
D
For PMOS, they are negative.
B
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Simple Model versus SPICE
2.5
x 10
-4
VDS=VDSAT
SPICE
2
Velocity
Saturated
I (A)
1.5
Model
D
Linear
1
VDSAT=VGT
0.5
VDS=VGT
0
0
0.5
Saturated
1
1.5
2
2.5
VDS (V)
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Transistor Model for Manual analysis
Parameters for manual model of generic 0.25 um CMOS process
(Minimum length device)
VT0(V)
(V0.5)
VDSAT(V)
k’(A/V2)
(V-1)
NMOS
0.43
0.4
0.63
115 x 10-6
0.06
PMOS
-0.4
-0.4
-1
-30 x 10-6
-0.1

Caution! Try to extrapolate the behavior of the device
other than W and L given in the table can lead to sizable
errors.

Digital Circuits usually use Minimum Length devices
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The Transistor Modeled as a Switch
Modeled as a switch with
infinite off resistance and
a finite on resistance, Ron
x105
VGS  VT
7
6
S
5
Ro
D
n
4
Resistance inversely
proportional to W/L (doubling
W halves Ron)

3
2
1
0
0.5
1
1.5
2
For VDD>>VT+VDSAT/2, Ron
independent of VDD

2.5
VDD (V)
Once VDD approaches VT,
Ron increases dramatically

(for VGS = VDD, VDS = VDD VDD/2)
VDD(V)
1
1.5
2
2.5
NMOS(k)
35
19
15
13
PMOS (k)
115
55
38
31
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Ron (for W/L = 1)
For larger devices
divide Req by W/L
46
B.Supmonchai
Dynamic Behavior of MOS Transistor
G
CGS
CGD
D
S
CGB
CSB
CDB
B
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MOS Transistor Capacitances
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Overlap Capacitances

Polysilicon gate

Drain
Source
xd
n+
xd
Ld
Cox 
W
t ox
ox
(F/m2)
n+
Gate-bulk
overlap
Cgso  Cgdo  Col
Top view
Col  Cox x d W  CoW
Gate oxide
tox
n+
L
n+
*Cfringe = (2ox/) ln (1+Tpoly/tox)
Cross section
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Gate-Channel Capacitances
G
G
D
S
G
D
S
D
S
B
B
B
Cut-off
Resistive
Saturation
Most important regions in digital design: saturation and cut-off
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Variation of Gate-Channel Capacitances
CG C
WLC ox
WLC ox
CGC B
C G CS = CG CD
2
VT
VG S
Capacitance as a function of VGS
(with VDS = 0)
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WLC ox
CG C
2WLC ox
CG CS
WLC ox
2
3
CGCD
0
VDS /(VG S-VT)
1
Capacitance as a function of the
degree of saturation
MOS Transistor Theory
51
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Diffusion Capacitances
Gate
5
4
SiO2
1
3
p
n+
2
W
xj
LS
Substrate
Cdiff  CBottom  CSidewall  C1  (C2  C3  C4  C5 )
Cdiff  C j LSW  C jsw (2LS  W )

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Junction Capacitance: Recap
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Linearizing the Junction Capacitance
Replace non-linear capacitance by
large-signal equivalent linear capacitance
which displaces equal charge
over voltage swing of interest
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MOS Transistor Capacitance: Summary
Gate
CGS = Cgs + Cgso
CGD = Cgd + Cgdo
Source
Drain
CGB = Cgb
CDB = Cdiff
CSB = Cdiff
Body
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Capacitances in 0.25 m CMOS process
Capacitance parameters of NMOS and PMOS transistors in 0.25 m CMOS process.

For an NMOS transistor with tox = 6 nm, L = 0.24 m,
W = 0.36 m, LD = LS = 0.625 m
 Total Gate Capacitance CG = Cg + 2Col = 0.7 fF
 CSB = CDB = 0.89 fF
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
B.Supmonchai
Parasitic Resistance
G
G
D
S
VGS,eff
RS
RS
RD
D
LD
Drain
contact
Drain
RD
RS,D
Drain
contact
W
S
LD
Polysilicon gate
W
VGS,eff
Polysilicon gate
LS,D

Rsq  RC
W
Drain
Rsq = Sheet Resistance per square (20 - 100 ohms/sq.)
RC = Contact Resistance
Careless Layout may lead to resistances that severely degrade
device performance.
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The DSM MOS Transistor

Secondary Effects become more pronounce in
the deep-submicron transistor.
 Threshold Variations
 Hot Carrier Effects
 CMOS Latchup

Designing the circuits with all secondary effects
taken into account is intractable and results can
be obscure.

Analyze with first-order model, then readjust the
model with the help of CAD simulation tools.
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Threshold Variations
VT
VT
Long-channel
threshold
Low VDS threshold
Short-channel
threshold
VDS
L
Threshold as a function of the
length (for low VDS)
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Drain-induced barrier lowering
or DIBL (for low L)
MOS Transistor Theory
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B.Supmonchai
Hot Carrier Effects

Electrons become “hot”, i.e. reaching a critical
high level of energy, under intense electric field
which occurs when the channel is short.
 Ecrit ≈ 104 V/m

Hot electrons can leave the silicon and tunnel
into the gate oxide.

Electrons trap in the gate oxide increase NMOS
threshold and decrease PMOS threshold.

Hot electron phenomenon leads to a long-term
reliability problem.
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B.Supmonchai
CMOS Latch-up
VDDVDD
p+
+
p+ n
+
+ p+
n+ n n
+
p+ p
VD DVD D
Rnwell
Rnwell
+
p+ n n+
p-source
p-source
n-well
Rnwell
n-well Rnwell
Rpsubs
Rpsubs
p-substrate
p-substrate
(a) Origin
of latchup
(a) Origin
of latchup
n-source
n-source
Rpsubs
Rpsubs
(b) Equivalent
circuit
(b) Equivalent
circuit

Latchup causes positive feedback of the current until the
circuit fails or burns out.

To avoid Latchup, Rnwell and Rpsubs should be minimized.

Devices carrying a lot of current need Guard Rings.
2102-545 Digital ICs
MOS Transistor Theory
61
B.Supmonchai
Future Perspectives
25 nm FINFET MOS transistor
2102-545 Digital ICs
MOS Transistor Theory
62