Transcript TOG electronics

TOF Electronics
Qi An
Fast Electronics Lab, USTC
Sept. 16~17, 2002
Two Functions
• To provide a precision time measurement for
Particles Identification
• To provide an event timing signal used by
trigger system
• Time Resolution
 Total of TOF system: 80ps (RMS)
 Uncertainty from Electronics: 25ps (RMS)
TOF Readout Electronics
• Time Measurement
• Charge Measurement
• Mean Timer
TOF Signal Processing
PMT1
PMT2
176 × Barrel TOF
1:3 split
Leading Edge
Discrim.with
low threshold
1:3 split
Leading Edge
Discrim.with
high threshold
gate
L1 Trigger
HPTDC
Leading Edge
Discrim.with
high threshold
Mean Timer
ADC
Leading Edge
Discrim.with
low threshold
gate
ADC
HPTDC
L1 Trigger
To Trigger Module
TOF Signal Processing. For simplicity, only a signal sector is shown
Time Measurement
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Multi-Hit Capability
Time Resolution: 25 ps (RMS)
Dynamic Range: 60 ns
Discriminate with Double Threshold (Low & High)
HPTDC
HPTDC
– High Precision General Purpose TDC (HPTDC)
(J. Christiansen et al.)
– 32-channel TDC
• Bin 100, 200, 400 or 800 ps
• Dynamic range about 100 ms
– 8-channel TDC (Very High Resolution Mode)
• Bin 25 ps
• Same dynamic range
Architecture
• The Timing Unit
Based On A 40MHz Clock
 PLL
 DLL
 Coarse Counter
 RC-Delay Line
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• Data Processing Unit
Trigger Match
 L1 Buffer
 Read FIFO
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Performance Of HPTDC
Two Options for Time Measurement
• HPTDC Without Time Stretcher (TS)
- It will be our first choice
• HPTDC With Time Stretcher (TS)
- KEK’s TS Daughter
- Monolithic Integrated Time Stretcher (MTS1)
KEK’s Clocked Time Stretcher
HPTDC With Time Stretcher
• Principle of KEK’s Time Stretcher
• Feasibility of HPTDC with TS Scheme
▪ HPTDC Time resolution: 100ps
▪ Time Stretch: f = 4
▪ 4 Time Tags (T1, T2, T3 & T4) for One TOF Hit
▪ Simultaneous Measure Leading and Trailing Edge of
Signal with one channel of HPTDC
▪ Dead Time
- TS Daughter board: 400ns (included a recovery time)
- MTS1: No Dead Time with Ping Pang Mode
The Input & Output Signal of TS
• Input:
TOF Hit Signal and Reformance Clock
• Output: Time Tag: T1, T2, T3 and T4
Δt = T2-T1;
fΔt = T3-T2
Monolithic Time Stretcher (MTS1)
Technical Parameters of MTS1
• Process: Agilent 0.5 mm CMOS, 3 metal,
single poly, linear Capacitor
• 8 Channels: 8 LVDS inputs & 16 LVDS
outputs (2x 8 channels)
• Programmable Stretch factor: 1:1 to 1:20
(1:4 will be used in BESIII)
• Ping-Pong Mode
• RF clock: LVDS pair (up to 100MHz)
• Package: 84-pin TQFP Functions
Evaluation of HPTDC
• Three ways of testing
- HPTDC channel with KEK’s TS Daughter board
- HPTDC channel with Monolithic TS chip
- HPTDC channel without TS
• Test Board
- VME 6U
- A32, D32 Mode
- LVDS Inputs
Charge Measurement
• Functions
- To correct the Effect of Time Walk
• Two Options:
- Amplitude Measurement
- Waveform Digitization
Amplitude Measurement
PMT
Signal
FIFO
~3.2µs pipeline
Peak
Detect
Events
Buffers
VMEBus
12 Bits
FADC
Option 2: Waveform Digitizer
• Analog Transient Waveform Digitizer (ATWD)
(Designed by LBNL)
- Four Independent Channels
- Sample Rate : 0.3~2 GSPS
- Resolution: 10 Bit
- 128 Analog Memories
- 128 Wilkinson Type ADC with 40 MHz counter clock
• Ping Pang Mode to Reduce the Dead Time
Ping Pang Mode
AWTD A
4 PMT signals
Output
4 2:1
MUX
Buffer
ADC Output Data
AWTD B
4 Disc. Outputs
L1 Trigger
Trig. Logic
Control Logic
40MHz Reference Clock
• Using RF Clock as t0 instead of “Pick Up” signal for the
beam collision time
• Getting a 40MHz clock from RF signal as a reference
clock for HPTDC & others
• The Jitters should be less than 20ps RMS
Design Strategies for 40MHz Clock
• Using PLL technique to generate 40MHz clock and clean
up the input clock.
• Using an optical transfer system with 80m Phase Stabilized
Optical Fiber (PSOF) .
• Using low skew & low jitter clock driver for clock
distribution.
Block diagram of reference clock system
PLL: SY89421V
SY89421V Precision PLL (Micrel Semiconductor)
– Input Range:
• 12MHz-560MHz with internal VCO operation
• 2GHz with HF Inputs and External VCO
– Output Range:
• >1GHz with Internal VCO
• 2.0GHz with External VCO
– Two Output Pairs:
• HF Outputs (VCO Output)
• F Outputs (post dividers)
– External Loop Filter
– Jitter: 10ps RMS (Typ), 15ps RMS (Max)
– Internal programmable dividers offer 1-40 range.
40MHz clock Circuit
SY89421V
RF Signal Input
Phase
500MHz
VCO
HFout
Detector
P-Div
N-Divider
1, 2
1,2,4,8,10,12,16,20
N Divider = 12
P-Divider = 1
Fout = Fin /12 =40MHz
Fout
40MHz
Clock Out
NB100LVEP221
Clock Fanout: 1:20
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85 ps Typical Device–to–Device Skew
20 ps Typical Output–to–Output Skew
Jitter Less than 1 ps RMS
Maximum Frequency > 1.0 GHz Typical
Thermally Enhanced 52–Lead LQFP
VBB Output
540 ps Typical Propagation Delay
LVPECL & HSTL Mode
LVECL Mode
Test Board for PLL & Fannout
NB100LVEP221 X2
On Board 500MHz Clock
O1
O2
O3
PLL
SY89421
Crystal
1
500MHz
MUX
Input RF
PLL
40MHz
SY89421
0
500MHz Clock
O40
Control Logic
Clock Fanout
Total Electronics Requirements
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FEE Boards (16 ch/board):
Leading Edge Discriminators :
Trigger Outputs :
TDC Channels :
ADC Channels :
Pre_Amplifiers:
28
896 (HL & LL)
272
448
448
176 ( If CTTs are used )
Thanks