Transcript Memory Definitions

CPEN 315 - Digital System Design
Chapter 8 – Memory
C. Gerousis
© Logic and Computer Design Fundamentals, 4rd Ed., Mano
Prentice Hall
Charles Kime & Thomas Kaminski
© 2008 Pearson Education, Inc.
Overview
 Memory definitions
 Random Access Memory (RAM)
 Static RAM (SRAM) integrated circuits
– Cells and slices
– Cell arrays and coincident selection
 Arrays of SRAM integrated circuits
 Dynamic RAM (DRAM) integrated circuits
 DRAM Types
– Synchronous (SDRAM)
– Double-Data Rate (DDR SRAM)
– RAMBUS DRAM (RDRAM)
Memory Definitions
 Memory ─ A collection of storage cells together with
the necessary circuits to transfer information to and
from them.
 Random Access Memory (RAM) ─ RAM is called
"random access" because any storage location can
be accessed directly (independent of the physical
location of the data.)
 Memory Address ─ A vector of bits that identifies a
particular memory element (or collection of
elements).
Memory Definitions (Continued)
 Typical data elements are:
– bit ─ a single binary digit
– byte ─ a collection of eight bits accessed together
– word ─ a collection of binary bits whose size is a
typical unit of access for the memory. It is typically
a power of two multiple of bytes (e.g., 1 byte, 2
bytes, 4 bytes, 8 bytes, etc.)
 Memory Operations ─ operations on memory
data supported by the memory unit. Typically,
read and write operations over some data
element (bit, byte, word, etc.).
Memory Organization
 Organized as an indexed array of words. Value of the
index for each word is the memory address.
 Some historically significant computer architectures
and their associated memory organization:
– Digital Equipment Corporation PDP-8 – used a 12-bit address
to address 4096 12-bit words.
– IBM 360 – used a 24-bit address to address 16,777, 216 8-bit
bytes.
– Intel 8080 – (8-bit predecessor to the 8086 and the current Intel
processors) used a 16-bit address to address 65,536 8-bit bytes.
Historical Computers
DEC PDP-8
Intel 8080, 4,500 transistors
IBM 360
Memory Organization Example
 Example memory
contents:
Memory Address
Binary Decimal
– A memory with 3
000
0
address bits & 8 data
001
1
bits has:
010
2
– k = 3 and n = 8
011
3
 23 = 8 addresses
100
4
labeled 0 to 7.
101
5
11 0
6
– 23 = 8 words of 8-bit
111
7
data (1-byte data)
Memory
Content
10001111
11111111
10110001
00000000
10111001
10000110
00110011
11001100
Static RAM
Cell
 Array of storage cells used to implement static RAM
Select
 Storage Cell
– SR Latch
– Select input for
control
– Dual Rail Data
Inputs B and B
– Dual Rail Data
Outputs C and C
B
B
S
Q
R
Q
C
C
RAM cell
SRAM is used in cache: temporary storage area where
frequently accessed data can be stored for rapid access.
Static RAM
Cell
2n-Word  1-Bit RAM IC
 To build a RAM IC
from a RAM slice,
we need:
– Decoder decodes
the n address lines to
2n word select lines
– A 3-state buffer
on the data output.
A3
A3
A2
A2
A1
A1
A0
A0
16 x 1
RAM
Data
output
Data
input
Read/
Write
Word select
4-to-16
Decoder 0
1
23
2
RAM cell
3
22
4
5
21
6
RAM cell
0
7
2
8
9
10
11
12
13
14
15
RAM cell
Memory
enable
Read/Write
logic
(a) Symbol
Data input
Data in
Data out
Read/ Bit
Write select
Read/Write
Chip select
(b) Block diagram
Data
output
Cell Arrays and Coincident Selection
 Memory arrays can be very large
– Large decoders
– The decoder size and fanouts can be reduced by
approximately n by using a coincident
selection in a 2-dimensional array
– Uses two decoders, one for words and one for
bits
– Word select becomes Row select
– Bit select becomes Column select
Cell Arrays and Coincident Selection
(continued)
Example
For address 1001:
10 selects row 2
01 selects column 1
Cell 9 is accessed.
A3
Row decoder
2-to-4
Decoder
0
21
A2
20
RAM cell
0
RAM cell
1
RAM cell
2
RAM cell
3
RAM cell
4
RAM cell
5
RAM cell
6
RAM cell
7
RAM cell
8
RAM cell
9
RAM cell
10
RAM cell
11
RAM cell
12
RAM cell
13
RAM cell
14
RAM cell
15
Read/Write
logic
Read/Write
logic
Read/Write
logic
Read/Write
logic
Data in
Data out
Read/ Bit
Write select
Data in
Data out
Read/ Bit
Write select
Data in
Data out
Read/ Bit
Write select
Data in
Data out
Read/ Bit
Write select
1
Row
select
2
3
Data input
Read/Write
X
X
X
X
Column select
0
Column
decoder
1
2
3
2-to-4 Decoder
with enable
21
20
A1
A0
Enable
Chip select
Data
output
Making Larger Memory
Capacity: 64K words of 8 bits each
256K X 8 RAM (2 MB)
- Three-state outputs are connected
together to form 8 data output lines.
- Just one chip select (CS) will
be active at any time.
- RAM requires 18-bit address:
16 LSB address are applied to the address
are applied to the inputs of each RAM.
2 MSB are applied to 2-to-4 decoder.
- Address bits 16 and 17 determine the
particular chips that is selected.
Dynamic RAM (DRAM)
 Basic Principle: Storage of information on
capacitors.
 Charge and discharge of capacitor to change
stored value
 Use of transistor as “switch” to:
– Store charge
– Charge or discharge
Select
B
T
C
DRAM cell
Dynamic RAM - Bit Slice
 C is driven by 3-state
drivers
 Sense amplifier is used
to change the small
voltage difference on C
into H or L  “to
refresh the value of a
bit stored in a DRAM
cell.”
Select
Word
select
0
Word
select
0
T
B
DRAM cell
Word
select
1
C
DRAM cell
DRAM cell
Word
select
2n -1
Word
select
2n - 1
DRAM cell
T
B
C
Read/Write
logic
Data in
Data out
Read/
Bit
Write
select
Sense
amplifier
Data in
Write logic
Read/
Write
Bit
select
(a) Logic diagram
Read logic
Data out
DRAM VS. SRAM
 Cell size
 Complexity
 Cost/bit
 Usage in large memory
 Power considerations
 Speed
memory access time increases
physical size of memory decreases
Memory Hierarchy
DRAM Types
 Types to be discussed
– Synchronous DRAM (SDRAM)
– Double Data Rate SDRAM (DDR SDRAM)
– RAMBUS® DRAM (RDRAM)
Synchronous DRAM
 Transfers to and from the DRAM are synchronize with a
clock
 Comparison of byte rate for reading bytes from SDRAM to
that of basic DRAM:
Assume READ cycle time of basic DRAM = 60 ns
DRAM byte rate (Memory Bandwidth)
= 16.67 MB/sec
Clock period of SDRAM = 7.5 ns
SDRAM = 66.67 MB/sec
 If the read burst = 8 bytes,
What is the read cycle? 90 ns
What is the byte rate for
the SDRAM? 88.89 MB/sec
SDRAM EXAMPLE
Double Data Rate Synchronous
DRAM (DDR SDRAM)
 Transfers data on both edges of the clock
 Example: Same as for synchronous DRAM
– Read cycle time = 60 ns, read burst = 8 bytes.
– for DDR  ___
16 bytes can be transferred in 60 ns?
What is the Byte Rate/
Memory Bandwidth?
RAMBUS DRAM (RDRAM)
 Uses a packet-based bus for interaction between the RDRAM ICs and the
memory bus to the processor
 The bus consists of:
– A 3-bit row address bus
– A 5-bit column address bus
– A 16 or 18-bit (for error correction) data bus
 The electronic design is sophisticated permitting very fast clock speeds
Use clock period 1.875 ns
time for accessing 16 byte data
packet = 32 clock cycles.
What is the Memory Bandwidth ?
If four packed are accessed, what
is the memory bandwidth?