Transcript signal

Course Introduction
Digitalkonstruktion
Digital Electronics Design
Lecturer/Examinator:
Alf Johansson Senior Lecturer, Embedded Systems
[email protected]
0705-43 98 44 / 10 16 04
All documents are stored in the PingPong activity:
Digital Electronics Design 5p –HT06
Material also available on K:\elektro\digital design 06
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Digital Electronics Design
Course introduction
Kurslitteratur på svenska:
VHDL för konstruktion
Lennart Lindh, Stefan Sjöholm.
Studentlitteratur (ISBN 9144024711)
Litterature in English:
[1] VHDL for designers
Stefan Sjoholm/Lennart Lindh
Prentice Hall (ISBN 0134734149)
[2] Programmable Logic Design Quick Start Handbook
Karen Parnell and Nick Mehta
Xilinx Inc 2003
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Digital Electronics Design
Course introduction
Reference books:
VHDL-Cookbook
Peter Asheden
.pdf-file
Designers Guide to VHDL
Ashenden, Peter
Elsevier, UK, 2000 (ISBN 1558606742)
More in PingPong and on K:-drive e.g. VHDL.hlp
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Digital Electronics Design
Course Introduction
Schedule
Lectures/exercises(3p):
Labs/Projects(2p):
Tuesdays 8– 12
Tuesdays 13 - 17
Examination
Written exam + labs + project.
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Digital Electronics Design
1. Course introduction. Digital Electronics Design
Week
Lecture
Ref
Exercise
Lab
1/W35
Introduction
Concurrent VHDL
Programmable logic intro
[1] Chap
1-3
[2] Chap 1
Chap 3: 3, 4, 5, 10,
13, 14
Lab 1, Concurrent
VHDL
2/W36
Sequential VHDL
Chap 4
Chap 4: all
Lab 2, Sequential
VHDL
3/W37
Library, structural VHDL. State
machines FSM
Chap 5, 6, 9
Chap 5: 4,7,8,9
Chap 6: 1,2,6
Chap 9: 1,2,4,5,9
Lab 3
State machines
4/W38
Test benches
Chap 8,10,11,12
Chap 8: 1,3,4,5
Lab 4
Test benches
5/W39
Coding style. Design hints.
Project example.
Introduction to project..
Chap 13,14
Project
6/W40
Design tools ASIC technology
Test
Chap 15,16
Project
7/W41
Behavioural synthesis. SoC
Chap 17
Project
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Digital Electronics Design
Introduction
Design Method
Implementation
Schematics drawn
manually
Descrete components
were placed and routed
manually
1
2
&
3
IC 1:a
4
5
&
6
IC 1:b
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Digital Electronics Design
Introduction
Implementation
Design Method
Schematics drawn
with a CAD system
&
&
Discrete components were placed
and routed manually or
automatically by CAD tool.
Programmable logic like CPLDs
CPLD
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Digital Electronics Design
Introduction
Design Method
Implementation
HDL for design
entry
Synthesis of HDL to
generate a netlist.
Place&route tool to
implement in CPLD or
FPGA (or ASIC)
entity gates is
port(a,b,c: in std_logic;
d: out std_logic);
architecture rtl of gates is
begin
d<=a and b and c;
end rtl;
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Digital Electronics Design
Introduction
Custom Designed Integrated
Circuits and Programmable Logic
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Digital Electronics Design
Customer Designed
Integrated Circuits
Field programmable
ASIC
MGA
Std Cell
Full Custom
SOC
SOC
FPGA
105-107
gates
ASIC = Application Specific Integrated Circuit
MGA = Mask Gate Array = Prefabricated wafer with
logic+added interconnections (metal layers). Vol > 10k
Standard Cell = Library with components (e.g. gates,
multiplexors, flip-flops). Precompiled on transistor
level. Vol >100k
Full Custom = Transistor level design. Used for analogue
circuits.
SOC = System On Chip (processors, memories, logic)
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PLD
CPLD
102-103
gates
PLD
FPGA = Field Programmable Gate
Array. >1 milj gates!
PLD = Programmable Logic Device
CPLD = Complex PLD. <10k gates
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Digital Electronics Design
Moore’s law
Moore’s law:
108
The capacity ( e.g. # of gates) of integrated
chips doubles every 18-20 months.
circuits
tools
gap
106
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Digital Electronics Design
FPGAs in the future?
• Miljons of gates. 10 miljon gates circuits soon
available.
• Lower cost. Now 100k gates cost <$10.
• Soft IP (microcontrollers, DSPs, etc ) IP=Intellectual
Properties.
• FPGAs with hard IP cores. E.g. microcontrollers and
FPGA in one circuit (SOPC) .
• SOPC, System On Programmable Chip.
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Digital Electronics Design
Design Process
We need a more efficient way to design than using a
schematic tool
In software programmers became more productive when they
changed from Assembly language to a high level language
e.g. C
We want to model the behavior of the system and use tools to
translate to electronic blocks
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Digital Electronics Design
Modeling Digital Systems
• VHDL is for writing models of a system
• Reasons for modeling
 requirements specification
 documentation
 testing using simulation
 synthesis
• Goal
 most reliable design process, with
minimum cost and time
 avoid design errors!
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Digital Electronics Design
Domains and Levels of Modelling
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Digital Electronics Design
Domains and Levels of Modelling
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Digital Electronics Design
Domains and Levels of Modelling
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Digital Electronics Design
Domains and Levels of Modelling
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Digital Electronics Design
Motivation for HDL
(Hardware Description Language)
•
More and more complex circuits require efficient design and
verification methods.
• Technology independent. We have a rapid change in technology.
•
Design on a higher abstraction level and automatic
”codegeneration” (synthesis).
•
Standardised HDL enables use of IPs, Intellectual Properties.
•
Design and verification/test in one environment (language).
•
Using a HDL for design is as natural as using C or ADA instead of
assembler.
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Digital Electronics Design
VHDL
VHSIC Hardware Description Language
(VHSIC=Very High Speed Integrated Circuit)
• Initiated by DoD (Department of Defense) early
1980s
• Specified by Intermetrics (they also specified
ADA)
• Standard IEEE 1076-1987 (VHDL-87, VHDL-93,
VHDL-2002)
•VHDL-2000,
Standard language
for specification and modelling
• Subset of language for synthesis
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Digital Electronics Design
Basic VHDL Concepts
• Interfaces
• Behaviour
Design
• Structure
• Test Benches
• Analysis, elaboration, simulation
• Synthesis
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CAD
tools
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Digital Electronics Design
Why use VHDL ?
•
Technology independent => Technologies change during the life time of electronic
products. Use automatic tools to implement new technologies.
•
Modifiability => Easy to read, hierarchical and structured.
•
Hierarchical => Structural VHDL (block diagrams).
•
Abstraction levels => Behaviour, RTL and gate level.
•
Supports concurrent and sequential language constructions (C only sequential).
•
Reuse of designs and part of designs => components.
•
Can be verified in a (technology independent) simulator.
•
De facto standard for design (synthesis) => Synopsys.
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Digital Electronics Design
History
1
Signal
generator
Prototype
Oscilloscope
Verification with ”black box” prototype
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Digital Electronics Design
History
2
Input signal file
”signal gener.”
Computer model.
Netlist prototype.
Output signal file
”logic analyser”
Verification with a schematics in the computer
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Digital Electronics Design
History
3
VHDL
Synthesis
Netlist
Prototype
model
Input signal file
”signal gener.”
Output signal file
”logic analyser”
Synthesis to gates and flip-flops
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Digital Electronics Design
History
4
A
Computer
VHDL
”prototype”
VHDL component
”signal gener.”
B
VHDL component
”logic analyser”
Verification with a testbench (A and B) in the computer
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Digital Electronics Design
Synthesis
• Synthesis = Translate VHDL to logic
• Logic synthesis = Translate Boolean functions to gates
•RTL synthesis (Register Transfer Level) = Logic synthesis + sequential
constructs to gates and flip flops. All clocking defined by designer.
• Behavioral synthesis = reuse of components (e.g. a common
multiplier). Clocking defined by synthesis tools.
Technology
Synthesis
a
mapping
process(sel,a,b)
begin
if sel=’1’ then
c<=b;
else
c<=a;
end if;
end process;
sel
a
b
0
sel
1
&
c
1
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c
1
b
&
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Digital Electronics Design
VHDL abstraction levels
Functional
level
System
Behavioural
level
RTL level
clk
res
Logic level
&
&
&
Computer
model
information
Higher abstraction levels conceal details.
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Digital Electronics Design
Design domains and abstraction levels in Y Charts
Behavioral
domain
Structural
domain
Processors, mem
Functional
design
Registers, ALUs
Algorithms
Behavioral
RTL
Gates, Flip-Flops
Boolean
Transistors
Transistor functions
Transistor layout
Cells, modules
Physical design
of chips
More details when we
move towards center
Physical
domain
Chips, ASICs
Boards, MCM
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Digital Electronics Design
Design Process Representation in Y- Chart
Structural domain
Behavioral
domain
netlist
Processors, mem
Synthesis
Algorithms
Behavioral (VHDL)
Registers, ALUs
RTL (VHDL)
Gates, Flip-Flops, muxes, adders
Gates, FF
Transistors
Implementation
(technology mapping)
Boolean
Transistor functions
Transistor layout
Cells, modules
e.g. bit file
Physical
domain
Chips, ASICs
Boards, MCM
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Digital Electronics Design
Peter Asheden
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Digital Electronics Design
VHDL abstraction levels and hierarchies
Abstraction levels:
•
Behavioural level: Reuse of instantiated components. No architecture is required.
Research area. Few tools on market.
•
RTL (Register Transfer Level): Logic + sequential circuits like registers and
state machines. At RTL all registers are defined in VHDL code.
•
Logic level: Boolean algebra or gate network.
•
Compare abstraction levels with programming languages:
UML – C – assembler –machine code
Comp1
Design hierarchies:
Comp21
•
Comp22
Complexity not reduced but easier
to understand.
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Digital Electronics Design
VHDL
• VHDL components: Central concept in VHDL. The components can be
stored in libraries. A component can be a simple gate or a complex system
like a microprocessor. The internal behavior can be concealed from the
designer (black box) and only the component interface is shown.
• Entity: The entity declaration defines the interface between an entity and
the environment. The entity name is the same as the component name.
• Architecture: An architecture defines the body of a component entity and
specifies the behavior between inputs and outputs. An architecture is tied
to one entity and one entity can have several architectures.
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Digital Electronics Design
-- ****************************************
-- My first VHDL program
-- Kundanpassade kretsar HT 2001
-- ****************************************
The entity describes
the boarder of a
component
library ieee;
use std_logic_1164.all;
use std_logic_unsigned.all;
Two hyphens -- indicate start of
a comment for the rest of a line
library for signal types
entity and_gate is
Component name:
and_gate
Let’s make a very
simple VHDL
program
port (a,b: in std_logic,
c: out std_logic);
end;
port describes the input
and output signals of a
component.
a and b are input signals
c is an output signal
std_logic describes
signal type
architecture rtl of and_gate is
begin
c <= a and b;
architecture
describes what
shall be done
rtl is an arbitrary name
of an architecture
end rtl;
Signal c is assigned the boolean
and of a and b
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Digital Electronics Design
VHDL Syntax
Example
entity ex is
port (a,b: in std_logic;
c: out std_logic);
end ex;
Syntax (VHDL-93)
entity <identifier_name> is
port ([signal] <identifier>:[mode]<type_indicator>;
[signal] <identifier>:[mode]<type_indicator>;
……
[signal] <identifier>:[mode]<type_indicator>);
end [entity] <identifier_name>;
<mode> = in, out, inout, buffer
in:
input signal to component
out:
output signal from component
inout:
bidirectional signal
buffer:
output signal that can be read (out signal can’t be read!!!)
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Digital Electronics Design
VHDL Syntax
-- Example
entity ex is
port (a,b: in std_logic;
c: out std_logic);
end ex;
architecture rtl of ex is
begin
c <= not (a and b);
end rtl;
Syntax (VHDL-93)
architecture <architecture_name> of <entity_identifier> is
[<architecture_declarative_part>]
begin
<architecture_statement_part>
end [architecture] <architecture_name>;
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Digital Electronics Design
Logical operators
not
and
nand
or
nor
xor
xnor
inverted
a<=not b;
a<=b and c;
a<=b nand c a<=not(b and c);
a<=b or c;
a<=not(b or c);
a<=not((b and c) or (not b and not c));
a<=(b and c) or (not b and not c); (VHDL –93)
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Digital Electronics Design
The three faces of VHDL
VHDL has three different parts:
• Concurrent VHDL (Parallell VHDL)
• Sequential VHDL (Sekventiell VHDL)
Behavioral
• Structural VHDL (Strukturell VHDL)
Some constructs are only allowed in the concurrent part other
constructs only in the sequential part. The syntax may differ in the
different parts ( in order to show the differences).
The timing is different in concurrent and sequential VHDL
Concurrent
Sequential
with xx select
q<=a when ”00”,
b when ”11,
’0’ when others;
case xx is
when ”00” => q<=a;
when ”11” => q<=b;
when others => q<=’0’;
end case;
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Digital Electronics Design
Concurrent VHDL
The nature of hardware is parallel. A HDL must have features to describe the parallel
behavior of hardware. In VHDL this is called ”concurrent VHDL”.
Signal assignment
Think of signals as physical connections
Examples: a<=’0’; a<=b after 10 ns; a<=b and c; a<=’0’, ’1’ after 20 ns, b after 30 ns;
Syntax (VHDL –93)
Signal assignment:
<target_identifier>’<=’ <selected_expression>’;’
Syntax (VHDL –93)
Signal assignment with delay:
<target_identifier>’<=’ <selected_expression> ’after’ 10 ’ns’ ’;’
NB ”after” can’t be synthesised and is dismissed by synthesiser.
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Digital Electronics Design
Concurrent VHDL. Delays
• Inertial delay (tröghets): Default in VHDL. Spikes are not propagated (if ’after’ is used).
Often used in electronic component delays.
• Transport delay: Pulses are always propagated. Used for delay lines.
• Reject delay: Is used when spike filtering is not the same as the circuit delay (VHDL-93).
• Inertial delay is ignorded by synthesis tools. Transport delay will give errors (often).
a
b
b1
a
b2
10
20
30
40
50
60
b3
70 [ns]
b1 <= a inertial after 10 ns;
b2 <= a transport after 10 ns;
b3 <= a reject 4 ns inertial after 10 ns;
a
10
20
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30
40
50
60
70
80 [ns]
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Digital Electronics Design
Concurrent VHDL. Assignment order
• Concurrency: Hardware is parallel in nature. VHDL has constructions for
concurrency (e.g C has not but SystemC has).
• Concurrent constructions in VHDL are executed concurrently and the order in
which the code is written is irrelevant.
• Concurrent commands in VHDL are event-controlled.
architecture rtl of ex1 is
begin
c <= b;
b <= a;
end rtl;
a
b
c
architecture rtl of ex2 is
begin
b <= a;
c <= b;
end rtl;
a
b
c
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Digital Electronics Design
Concurrent VHDL. Delta time
• Delta time is used for queuing up sequential events. Delta times are executed while the
simulation clock is stopped. When combinational logic has 0 ns delay the simulator counts
up one delta time for each assignment. The delta time will count up until all signals are
stable.
• What happens with the assignment: q <= not q; ??
D<= not C;
C<=A and B;
30 ns+2 delta
A
C
&
B
D
D
30 ns+1 delta
A
57 ns+1 delta
C
B
10
57 ns+2 delta
20
30
40
50
60
70 [ns]
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10
20
30
40
50
60
70 [ns]
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Digital Electronics Design
Concurrent VHDL. When statement
-- Example
architecture rtl of ex is
begin
q<= a when data=”00” else
b when data=”11” else
c;
end rtl;
Syntax
When statement:
<target>’<=’ <expression> [after <expression>] when <condition> else
<expression> [after <expression>];
Several when else lines can be used!
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Digital Electronics Design
Concurrent VHDL. When statement
-- Example
-- Useful when statement
architecture rtl of three_state is
begin
dbus0<= data0 when enable=’1’ else
’Z’;
end rtl;
enable
data
dbus
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Digital Electronics Design
Concurrent VHDL. With statement
-- Example
architecture rtl of ex is
begin
with data select
q<=a when ”00”,
b when ”11”,
c when others;
end rtl;
Syntax
With statement:
with <expression> select
<target>’<=’ <expression> when <choose>;
<expression> when <choose>;
All possible <choices> must be enumerated!
Remaining choices can be collected in when others!
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Digital Electronics Design
Concurrent VHDL. Object, class and type
Class
signal
Object
a:
Type
std_logic;
Std_ulogic/std_logic:
’U’ – uninitialized (start value=left)
Class
• constant
• variable
• signal ”a wire”, time dependent
’X’ – forcing unknown
constant a: std_logic_vector(3 downto 0):= ”1111”;
signal b: std_logic_vector(7 downto 0);
variable c: std_logic;
’Z’ – high impedence
Type
Datatypes to be used in this course:
’H’ – weak 1
’0’ – forcing 0
’1’ – forcing 1
’W’ – weak unknown
’L’ – weak 0
’-’ – don’t care
• integer NB: Length is implementation dependent!
Use range! signal my_int: integer range 0 to 255;
• std_ulogic
• std_logic (resolved type of std_ulogic).
Signal driver and resolve function (read the book!!).
Every signal assignment in concurrent
VHDL will create a driver. Two or more
assignments of the same signal require
resolved types.
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Digital Electronics Design
Concurrent VHDL
• Type declarations of std_logic_vector:
type std_logic_vector is array (natural range<>) of std_logic;
• Declaration.
signal a_vect: std_logic_vector(7 downto 0); -- normal way to write with MSB to the left
signal a_vect: std_logic_vector(0 to 7); -- LSB to the left
signal a_vect: std_logic_vector(7 downto 0);
a_vect<= ”10101010”; -- Note double quotation marks!
a_vect<= b_vect;
Slice of array
signal a_vect: std_logic_vector(7 downto 0);
signal b_vect: std_logic_vector(5 downto 0); -- length differs
a_vect(0)<= ’1’;
a_vect(0)<= b_vect(1);
a_vect(7 downto 1)<=a_vect(6 downto 0); --Left shift one step!
a_vect<=(1=>’0’, 4=>’0’, others =>’1’);
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Digital Electronics Design
Concurrent VHDL. Vector assignment
Concatination
signal a_vect: std_logic_vector(7 downto 0);
signal b_vect: std_logic_vector(5 downto 0); -- length differs
a_vect<=”00” & b_vect; -- add two msb
Aggregate
signal a_vect: std_logic_vector(7 downto 0);
a_vect<=(others=>’0’); -- a_vect>=”00000000”
a_vect<=(1=>’0’, 4=>’0’, others =>’1’);
Bit string literals
a_vect<=B”11110000”; -- B”1111_0000” more readable
a_vect<=X”FFA0”;
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Digital Electronics Design
Concurrent VHDL. Operators
Relational operators
=
equal
/= not equal
<
less than
>
greater than
<= less than or equal
>= greater than or equal
Arithmetic operators
+
addition
subtraction
*
multiplication
/
division
abs absolute value
rem remainder
mod modulus
** exponantiation
Can be used on integers and
std_logic_vectors
= and /= can be used on all defined
data types
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all
These operators are predefined for
integer and time.
If std_logic_vector shall be used the
operators must be defined in a
package e.g. std_logic_unsigned.
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Digital Electronics Design
Concurrent VHDL. Internal signal.
Init values
Left-hand values
Init in entity or architecture (Not for synthesis)
The default init value is the
left-hand value in the value
list.
entity ex is
port(a: in std_logic:=’0’;
b: out std_logic);
end;
e.g. for std_logic the init
value is ’U’.
No in, out etc!
Internal signals
architecture behv of ex is
signal i1: std_logic:=’1’;
signal i2,i3: std_logic:=’H’;
signal i4: std_logic_vector(3 downto 0):=”0000”;
begin
……..
end;
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Digital Electronics Design
Concurrent VHDL. Block statement
• The block statement can be used to make the text more readable.
• The scope of signals that are declared in a block is the block.
• Signals from a block can be loaded into the simulator as one unit.
• The block statement is a concurrent statement.
architecture behav of ex is
Block
signal a
declarations
begin
addr_decode: block
signal cs_b: std_logic;
signal addr: std_logic_vector(3 downto 0);
scope
begin
……..
end block;
end behav;
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Digital Electronics Design
Introduction to labexercises
Mentor HDesigner
VHDL
source
Compiler/
Simulator
Synthesis
Mentor Leonardo
Mentor Modelsim
Netlist (.edif)
Xilinx Foundation
Place &
Route
Load circuit
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Xilinx
CPLD/
FPGA
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Digital Electronics Design
VHDL Examples
Ex 1.
Design an XOR-gate with AND and OR functions (entity xorgate) that has 2 inputs
and one output. Use std_logic as signal type.
a
Q
b
a
b
Q
0
0
0
1
0
1
0
1
1
1
1
0
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Digital Electronics Design
VHDL Examples
Ex 2.
Design a multiplexor (entity MUX8) that has 8 inputs, 3 selection lines and 1
output. The output is three_state type. Use std_logic as signal type.
a0-a7
8
Q
s0-s2
3
E
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s3-s0
Q (E=’1’)
Q (E=’0’)
000
a0
Z
001
a1
Z
010
a2
Z
011
a3
Z
100
a4
Z
101
a5
Z
110
a6
Z
111
a7
Z
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Digital Electronics Design
VHDL Examples
Ex 3.
Design an inverter (entity openc) that has an output as in the figure below. Use
std_logic as signal type.
Vdd
Q
a
Vss
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a
Q
0
1
1
0
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Digital Electronics Design