Transcript lecture4_FPGA_tools

Introduction to
FPGA
Devices & Tools
ECE 545 – Introduction to VHDL
George Mason University
FPGA Devices
ECE 545 – Introduction to VHDL
George Mason University
World of Integrated Circuits
Integrated Circuits
Full-Custom
ASICs
Semi-Custom
ASICs
PLD
PAL
PLA
ECE 545 – Introduction to VHDL
User
Programmable
FPGA
PML
LUT
(Look-Up Table)
MUX
Gates
3
Two competing implementation approaches
ASIC
Application Specific
Integrated Circuit
• designs must be sent
for expensive and time
consuming fabrication
in semiconductor foundry
• designed all the way
from behavioral description
to physical layout
ECE 545 – Introduction to VHDL
FPGA
Field Programmable
Gate Array
• bought off the shelf
and reconfigured by
designers themselves
• no physical layout design;
design ends with
a bitstream used
to configure a device
4
What is an FPGA?
Configurable
Logic
Blocks
Block RAMs
Block RAMs
I/O
Blocks
Block
RAMs
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Which Way to Go?
ASICs
FPGAs
Off-the-shelf
High performance
Low development cost
Low power
Short time to market
Low cost in
high volumes
ECE 545 – Introduction to VHDL
Reconfigurability
6
Other FPGA Advantages
• Manufacturing cycle for ASIC is very costly,
lengthy and engages lots of manpower
• Mistakes not detected at design time have
large impact on development time and cost
• FPGAs are perfect for rapid prototyping of
digital circuits
• Easy upgrades like in case of software
• Unique applications
• reconfigurable computing
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Major FPGA Vendors
SRAM-based FPGAs
• Xilinx, Inc.
• Altera Corp.
• Atmel
• Lattice Semiconductor
Flash & antifuse FPGAs
• Actel Corp.
• Quick Logic Corp.
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Xilinx

Primary products: FPGAs and the associated CAD
software
Programmable
Logic Devices


ISE Alliance and Foundation
Series Design Software
Main headquarters in San Jose, CA
Fabless* Semiconductor and Software Company



UMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996}
Seiko Epson (Japan)
TSMC (Taiwan)
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Xilinx FPGA Families
• Old families
• XC3000, XC4000, XC5200
• Old 0.5µm, 0.35µm and 0.25µm technology. Not
recommended for modern designs.
• High-performance families
• Virtex (0.22µm)
• Virtex-E, Virtex-EM (0.18µm)
• Virtex-II, Virtex-II PRO (0.13µm)
• Low Cost Family
•
•
•
•
Spartan/XL – derived from XC4000
Spartan-II – derived from Virtex
Spartan-IIE – derived from Virtex-E
Spartan-3
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Basic Spartan-II FPGA Block Diagram
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CLB Structure
COUT
G4
G3
G2
G1
Look-Up
Table O
Carry
&
Control
Logic
COUT
YB
Y
D
S
Q
CK
EC
Look-Up
Table O
R
F5IN
BY
SR
F4
F3
F2
F1
G4
G3
G2
G1
Carry
&
Control
Logic
YB
Y
D
S
Q
CK
EC
R
F5IN
BY
SR
Look-Up
Table O
Carry
&
Control
Logic
XB
X
CIN
CLK
CE
D
S
CK
EC
Q
F4
F3
F2
F1
R
SLICE
CIN
CLK
CE
Look-Up
Table O
Carry
&
Control
Logic
XB
X
D
S
Q
CK
EC
R
SLICE
• Each slice has 2 LUT-FF pairs with associated carry logic
• Two 3-state buffers (BUFT) associated with each CLB,
accessible by all CLB outputs
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CLB Slice Structure
• Each slice contains two sets of the
following:
• Four-input LUT
• Any 4-input logic function,
• or 16-bit x 1 sync RAM
• or 16-bit shift register
• Carry & Control
• Fast arithmetic logic
• Multiplier logic
• Multiplexer logic
• Storage element
•
•
•
•
Latch or flip-flop
Set and reset
True or inverted inputs
Sync. or async. control
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LUT (Look-Up Table) Functionality
x1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x1
x2
x3
x4
y
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
LUT
y
x1 x2 x3 x4
x1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
x3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
y
0
1
0
0
0
1
0
1
0
1
0
0
1
1
0
0
• Look-Up tables
are primary
elements for
logic
implementation
• Each LUT can
implement any
function of 4
inputs
x1 x2
y
y
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Distributed RAM
RAM16X1S
• A LUT equals 16x1 RAM
• Implements Single and DualPorts
• Cascade LUTs to increase
RAM size
• Synchronous write
• Synchronous/Asynchronous
read
• Accompanying flip-flops used
for synchronous read
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=
LUT
• CLB LUT configurable as
Distributed RAM
D
WE
WCLK
A0
A1
A2
A3
O
RAM32X1S
D
WE
WCLK
A0
A1
A2
A3
A4
LUT
=
LUT
or
O
RAM16X2S
D0
D1
WE
WCLK
A0
A1
A2
A3
O0
O1
or
RAM16X1D
D
WE
WCLK
A0
SPO
A1
A2
A3
DPRA0 DPO
DPRA1
DPRA2
DPRA3
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Shift Register
LUT
• Each LUT can be
configured as shift register
IN
CE
CLK
• Serial in, serial out
• Dynamically addressable
delay up to 16 cycles
• For programmable
pipeline
• Cascade for greater cycle
delays
• Use CLB flip-flops to add
depth
LUT
=
D
CE
Q
D
CE
Q
D
CE
Q
D
CE
Q
OUT
DEPTH[3:0]
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Shift Register
12 Cycles
64
Operation A
Operation B
4 Cycles
8 Cycles
64
Operation C
3 Cycles
• Register-rich FPGA 3 Cycles
9-Cycle imbalance
• Allows for addition of pipeline stages to increase
throughput
• Data paths must be balanced to keep desired
functionality
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Carry & Control Logic
COUT
YB
G4
G3
G2
G1
Y
Look-Up
O
Table
D
Carry
&
Control
Logic
S
Q
CK
EC
R
F5IN
BY
SR
XB
F4
F3
F2
F1
CIN
CLK
CE
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X
Look-Up
Table O
Carry
&
Control
Logic
S
D
Q
CK
EC
R
SLICE
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Fast Carry Logic
Each CLB contains separate
logic and routing for the fast
generation of sum & carry
signals
MSB
Carry Logic
Routing

• Increases efficiency and
performance of adders,
subtractors, accumulators,
comparators, and counters

Carry logic is independent of
normal logic and routing
resources
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LSB
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Accessing Carry Logic

All major synthesis tools can infer carry
logic for arithmetic functions
•
•
•
•
Addition (SUM <= A + B)
Subtraction (DIFF <= A - B)
Comparators (if A < B then…)
Counters (count <= count +1)
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Block RAM
Port B
Port A
Spartan-II
True Dual-Port
Block RAM
Block RAM
• Most efficient memory implementation
• Dedicated blocks of memory
• Ideal for most memory requirements
• 4 to 14 memory blocks
• 4096 bits per blocks
• Use multiple blocks for larger memories
• Builds both single and true dual-port RAMs
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Spartan-II Block RAM Amounts
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Block RAM Port Aspect Ratios
1
2
0
4
0
0
1k x 4
2k x 2
1023
4k x 1
1047
8
0
512 x 8
511
16
0
4095
255
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256 x 16
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Basic I/O Block Structure
D Q
EC
Three-State
FF Enable
Clock
SR
Three-State
Control
Set/Reset
D Q
EC
Output
FF Enable
Output Path
SR
Direct Input
FF Enable
Registered
Input
Q
D
EC
Input Path
SR
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IOB Functionality
• IOB provides interface between the
package pins and CLBs
• Each IOB can work as uni- or bi-directional
I/O
• Outputs can be forced into High Impedance
• Inputs and outputs can be registered
• advised for high-performance I/O
• Inputs can be delayed
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Routing Resources
CLB
CLB
PSM
CLB
CLB
PSM
CLB
PSM
CLB
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CLB
Programmable
Switch
Matrix
PSM
CLB
CLB
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Spartan-II FPGA Family Members
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Virtex-II 1.5V Architecture
Multipliers 18 x 18
Block RAMs
Multipliers 18 x 18
Block RAMs
Multipliers 18 x 18
Block RAMs
Multipliers 18 x 18
Configurable
Logic
Block
Block RAMs
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I /O
Block
Virtex-II 1.5V
Device
CLB
Array
Slices
Maximum
I/O
BlockRAM
(18kb)
Multiplier
Blocks
Distributed
RAM bits
XC2V40
8x8
256
88
4
4
8,192
XC2V80
16x8
512
120
8
8
16,384
XC2V250
24x16
1,536
200
24
24
49,152
XC2V500
32x24
3,072
264
32
32
98,304
XC2V1000
40x32
5,120
432
40
40
163,840
XC2V1500
48x40
7,680
528
48
48
245,760
XC2V2000
56x48
10,752
624
56
56
344,064
XC2V3000
64x56
14,336
720
96
96
458,752
XC2V4000
80x72
23,040
912
120
120
737,280
XC2V6000
96x88
33,792
1,104
144
144
1,081,344
XC2V8000 112x104 46,592
1,108
168
168
1,490,944
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Virtex-II Block SelectRAM
• Virtex-II BRAM is 18 kbits
• Additional “parity” bits
available in selected
configurations
WEA
ENA
SSRA
CLKA
DOA[# : 0]
DOPA[# : 0]
ADDRA[# : 0]
DIA[# : 0]
DIPA[# : 0]
Width Depth
1
16,386
Address
Data
Parity
[13:0]
[0]
N/A
WEB
2
8,192
[12:0]
[1:0]
N/A
ENB
RSTB
4
4,096
[11:0]
[3:0]
N/A
CLKB
DOB[# : 0]
DOPB[# : 0]
ADDRB[# : 0]
9
2,048
[10:0]
[7:0]
[0]
18
1,024
[9:0]
[15:0]
[1:0]
36
512
[8:0]
[31:0]
[3:0]
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DIB[# : 0]
DIPA[# : 0]
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FPGA Nomenclature
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FPGA Tools
ECE 545 – Introduction to VHDL
George Mason University
Design process (1)
Design and implement a simple unit permitting to
speed up encryption with RC5-similar cipher with
fixed key set on 8031 microcontroller. Unlike in
the experiment 5, this time your unit has to be able
to perform an encryption algorithm by itself,
executing 32 rounds…..
Specification (Lab Experiments)
VHDL description (Your Source Files)
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Functional simulation
entity RC5_core is
port(
clock, reset, encr_decr: in std_logic;
data_input: in std_logic_vector(31 downto 0);
data_output: out std_logic_vector(31 downto 0);
out_full: in std_logic;
key_input: in std_logic_vector(31 downto 0);
key_read: out std_logic;
);
end AES_core;
Synthesis
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Post-synthesis simulation
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Design process (2)
Implementation
Timing simulation
Configuration
On chip testing
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Design Process control from Active-HDL
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Simulation Tools
Many others…
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Synthesis Tools
… and others
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Logic Synthesis
VHDL description
Circuit netlist
architecture MLU_DATAFLOW of MLU is
signal A1:STD_LOGIC;
signal B1:STD_LOGIC;
signal Y1:STD_LOGIC;
signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;
begin
A1<=A when (NEG_A='0') else
not A;
B1<=B when (NEG_B='0') else
not B;
Y<=Y1 when (NEG_Y='0') else
not Y1;
MUX_0<=A1 and B1;
MUX_1<=A1 or B1;
MUX_2<=A1 xor B1;
MUX_3<=A1 xnor B1;
with (L1 & L0) select
Y1<=MUX_0 when "00",
MUX_1 when "01",
MUX_2 when "10",
MUX_3 when others;
end MLU_DATAFLOW;
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Features of synthesis tools
• Interpret RTL code
• Produce synthesized circuit netlist in a
standard EDIF format
• Give preliminary performance estimates
• Some can display circuit schematics
corresponding to EDIF netlist
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Implementation
• After synthesis the entire implementation
process is performed by FPGA vendor tools
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Translation
Synthesis
Circuit netlist
Electronic Design
Interchange Format
EDIF
Timing Constraints
Constraint Editor
Native
Constraint
File
NCF
UCF
User Constraint File
Translation
NGD
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Native Generic Database file
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Sample UCF File
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
#
# Constraints generated by Synplify Pro 7.3.3, Build 039R
#
# Period Constraints
#Begin clock constraints
#End clock constraints
# Output Constraints
# Input Constraints
# Location Constraints
# End of generated constraints
NET "clock" LOC = "P88";
NET "control(0)" LOC = "P50";
NET "control(1)" LOC = "P48";
NET "control(2)" LOC = "P42";
NET "reset" LOC = "P93";
NET "segments(0)" LOC = "P67";
NET "segments(1)" LOC = "P39";
NET "segments(2)" LOC = "P62";
NET "segments(3)" LOC = "P60";
NET "segments(4)" LOC = "P46";
NET "segments(5)" LOC = "P57";
NET "segments(6)" LOC = "P49";
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Pin Assignment
FPGA
P93
P88
P39
P42
P46
CLOCK
CONTROL(0)
CONTROL(1)
CONTROL(2)
RESET
LAB2
SEGMENTS(0)
SEGMENTS(1)
SEGMENTS(2)
SEGMENTS(3)
SEGMENTS(4)
SEGMENTS(5)
SEGMENTS(6)
P67
P62
P60
P48
P49
P50
P57
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Parallel Port Interface
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Constraints Editor
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Circuit netlist
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Mapping
LUT4
LUT1
FF1
LUT5
LUT2
FF2
LUT3
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Placing
FPGA
CLB SLICES
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Routing
FPGA
Programmable Connections
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Static Timing Analyzer
• Performs static analysis of the circuit
performance
• Reports critical paths with all sources of
delays
• Determines maximum clock frequency
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Static Timing Analysis
• Critical Path – The Longest Path From
Outputs of Registers to Inputs of
Registers
tP logic
in
D
Q
D
Q
out
clk
tCritical = tP FF + tP logic + tS FF
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Static Timing Analysis
• Min. Clock Period = Length of The
Critical Path
• Max. Clock Frequency = 1 / Min. Clock
Period
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Configuration
• Once a design is implemented, you must create a
file that the FPGA can understand
• This file is called a bit stream: a BIT file (.bit extension)
• The BIT file can be downloaded directly to the
FPGA, or can be converted into a PROM file
which stores the programming information
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Resources & Required Reading
Spartan FPGA devices
Xilinx Spartan-II 2.5V FPGA Family:
Complete Data Sheet
• Module 1: Introduction & Ordering Information
• Module 2: Functional Description
http://direct.xilinx.com/bvdocs/publications/ds001.pdf
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Resources & Required Reading
FPGA Tools
Integrated Interfaces: Active-HDL with Synplify®
http://www.aldec.com/Previews/active_synplify.htm
Integrated Synthesis and Implementation
http://www.aldec.com/Previews/synthesis_implementation.htm
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Hands-on Session
Enough Talking Let’s Get To It
!!Brace Yourselves!!
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MLU: Block Diagram
MUX_0
A1
A
IN 0
NEG_A
MUX_1
IN 1
MUX_2
Y1
IN 2
IN 3
Y
O U T PU T
S E L1
S E L0
B
B1
MUX_4_1
NEG_Y
MUX_3
NEG_B
L1 L0
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ALU Schematic
arith [1:0]
A[3:0]
B[3:0]
A+B
0
A-B
1
A <<< 1
2
A >>> 1
3
logic [1:0]
0
Y [3:0]
1
A and B
0
A or B
1
A xor B
2
A xnor B
3
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0
ar_log
1
neg_Y
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Questions?
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