Transcript Rad_damage_65nm - Indico

Radiation Damage Tests at
1GRad Dose on 65nm CMOS
transistors
Marlon Barbero – CPPM
Grzegorz Deptuch –FNAL
The RD53 collaboration
Plan
•
•
•
•
•
RD53 & CERN upgrades.
Effect of radiation on CMOS.
Few results on test transistors.
Few results on ICs and blocks.
Conclusion.
Rad Effects in 65nm, M. Barbero / G. Deptuch, Mai 23rd 2014
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RD53 collaboration
• “Development of pixel readout IC for extreme rate and
radiation” : ATLAS-CMS-CLIC working group on small
feature size electronics (focus on one 65nm techno so far).
• Goal:
– Small pixels.
– Very high hit rates.
– Very high radiation levels.
• Started with 1st meetings mid-2013.
• 6 working groups, among which one working group on
radiation effects (Bergamo-Pavia, CERN, CPPM, Fermilab,
LPNHE, New Mexico, Padova, but also others).
• The work presented here essentially done in this framework.
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Pixel detectors upgrades
ATLAS IBL
CMS Phase I
Nominal: 1-2 GHz.cm-2, 1GRad,
1016 neutrons.cm-2, typ 50×50μm2,
billion transistor 2×2 cm2 IC
ATLAS / CMS phase II
Main goal of this R&D!
Rad Effects in 65nm, M. Barbero / G. Deptuch, Mai 23rd 2014
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Radiation effects in CMOS
Rad Effects in 65nm, M. Barbero / G. Deptuch, Mai 23rd 2014
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Classical view of radiation effects
in MOS
• Focus here on the sensitive oxide (thin gate and FOX).
• Reminder:
– gate thickness 2.6nm.
– hole mobility is << than e- mobility.
Typical values (room T):
e ~ 20cm2 .V 1.s 1
 hole ~ 2.10 5 cm 2 .V 1.s 1

• 1st step: Radiation  e-/hole pair creation in oxide.
Depending on biasing, electrons swept out in ~ps. Still
fraction e- / holes recombine.
• 2nd step: Hopping hole transport to Si/SiO2 interface.
• 3rd step: Holes at interface  long-lived trap states.
• 4th step: Interface traps build-up.
ref: Oldham (ionizing radiation effects in MOS oxides)
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Notes on defect generation (I)
• Which hole fraction recombines initially = fn (density -particle
energy, particle type- and magnitude of field applied).
• Deep hole trapping (in transition region where oxidation is
incomplete). Annealing depends again on thickness, time,
temperature and applied field. Annealing process == either
tunneling (at ~ room temperature or below, neutralization by
electron to Si+) or thermal
excitation (higher temp.).
ΔV shift /
FB
Mrad dose
Flat-Band Shift /
Mrad dose function
of oxide thickness
in MOS cap
Rad Effects in 65nm, M. Barbero / G. Deptuch, Mai 23rd 2014
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oxide thickness [nm]
Notes on defect generation (II)
• Radiation-induced traps: Trivalent Si is passivated when oxide
is grown by H. But radiation (or other type of stress) 
depassivation (holes free proton reach interface and form H2
centers)== electrically active.
• Annealing (in particular in thin oxides) might cure deep hole
trapping component but not radiation-induced interface traps.
Vth vs annealing
ΔDit shift /
Mrad dose
Interface Traps
Density Increase /
Mrad dose function
ref: Schwank (physical mechanisms
Rad Effects in 65nm, M. Barbero
/ G. Deptuch,
Mai 23rd 2014
of oxide
thickness
contributing to device rebound)
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oxide thickness [nm]
Effect on drain current when
radiation in MOS structure
particle
metal
ionization
pos. charge trapped in oxide
e-/hole creation
fixed charge
oxide
surface states
surface states
silicon
ID 
1
W
Cox (VGS  VT ) 2
2
L
due to deep hole trapped + interface states
due to interface states
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Radiation Induced Narrow
Channel Effect -RINCE-
• Trapping in STI of rad-induced positive charges opens
inversion channel / parasitic transistor.
• Strong dependence on width of transistor: for narrow
transistors, influence of parasitic channels strong
competitor to main channel.
ref: Faccio (radiation induced edge effect
in deep submicron CMOS transistors)
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A word from the past
• CMS / ATLAS current Front-End:
– 250 nm technology.
– ~50 MRad.
– Use of enclosed layout + guard rings. Custom libraries!!! If
so, safe!
• ATLAS IBL (FE-I4):
– 130nm.
– ~250 MRad.
– Minimum W imposed. If so, safe!
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Effects on test transistors: results
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XRay irradiation at CERN
• XRay irradiation, 10 keV, 150 kRad.min-1
T = -25°C
T = -25°C
T = 25°C
T = 25°C
First day : T=25°C
Mohsine Menouni et al, CPPM
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T=100°C
T=100°C
NMOS threshold shift
•
A little decrease of the threshold for low dose level
– -20 mV shift for the minimum width device
•
For levels of dose > 200 Mrad, the absolute value of Vth increases
– At 1000 Mrad, the Vth shift is between 150mV to 320 mV depending on the
device width (maximum for 240nm/60nm)
•
The Vth recovery at room temperature is very slow
– Except at the beginning of annealing period and only for the narrowest
devices (W=120nm and W=240nm)
•
High Temperature annealing (100 °C for 7 days) :
– The Vth recovery is accelerated
– The global Vth shift is < 200 mV
– Reverse annealing behavior for the device with W=120nm (Vth first
decreases and increases after)
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Proton irradiation
• 3MeV proton -1016 neq.cm-2-, 3.6 - 36 MRad.min-1 ,
15
Lili Ding
et al, Padova.
Rad Effects in 65nm, M. Barbero / G. Deptuch, Mai 23rd 2014
nmos transconductance variation
T = -25°C
T = 25°C

After 1000 Mrad : KPN loss is between 20% and 40%

The GM recovery at room temperature is very slow

100°C annealing : KPN loss decreases to reach a values between 25% and 8%

The loss is still higher for narrower devices
T=100°C
Menouni, CPPM
Ding, Padova
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Notes on NMOS results
• Note 3MeV p (Padova) -1016 neq.cm-2- vs 10 keV Xray (CPPM).
• Note very different dose rate:
– 3.6 MRad.min-1 to 36 MRad.min-1 for Padova.
– 150 kRad.min-1 for CPPM / Xray box at CERN.
– Different time cst for building of Q in oxide vs interface  Does
this translate in much stronger influence of Qox contribution in
Padova’s case (compensating interface charges)?  annealing
studies!
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pmos transconductance variation
T = -25°C
T = 25°C
T=100°C
 For high level of dose (1000 Mrad), KPP decrease reaches 100% for 120 nm and 240nm
devices
 With annealing, devices recover the most part of GM loss
Menouni, CPPM
 Wider devices recovers practically the pre-irradiation GM value
 For the narrowest device, KPN variation is only 32% compared to the pre-irradiation value
pmos threshold shift
T = -25°C
T = 25°C
T=100°C
 Vth increases rapidly from a dose levels of 200 Mrad
 Vth shift is < 120 mV for 1000 Mrad for wider devices and cannot be
computed for narrower devices.
 Vth is still increasing with annealing (reverse annealing)
Menouni, CPPM
Effects on IC and blocks: results
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CPPM test of LBNL’s IC
Rows 0-255
Rows 0-255
• When CPPM tested SEU in LBNL-dvp’ed 65nm proto (CERN
PS)  Observed localized bits stuck in shift register used
for pixel config. loading.
390 MRad to 420 MRad
260 MRad to 310 MRad
• Hypothesis: TID effect /
Pattern 1111
Pattern 1111
Bit leaking.
• Narrow pmos dose effect?
Tests with 24 GeV
proton beam
Columns 0-15
Columns 0-15
CPPM / LBNL
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Test IC dvped by CERN
•
chip with digital logic blocks
• Assembled with foundry standard
cells, pads and IP blocks
• Packaged, functional tests &
irradiation measurements run on a
custom test board
– Shift-register
• 64 kbit, “DFQD1”
• MinW=150nm for both p and n
– Ring oscillator
• 1025 inverters “INVD0”
• Wn=195nm, Wp=260nm
– SRAM (from foundry compiler)
• 56 kbit
• MinW = 90nm
Ring oscillator
Shift-register
SRAM
Sandro Bonacini, CERN
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Low temp / high temp influence?
Bonacini, CERN
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1
Normalized frequency and current
0.95
frequency
0.9
current
0.85
0.8
0.75
0.7
Current and frequency normalized [%]
2011, @25C
0.65
0.6
0.0E+00
0.95
Current
Frequency
0.9
2014, @ –25C
0.85
0.8
0.75
0.7
0.65
5.0E+07
1.0E+08
1.5E+08
2.0E+08
0
2
4
dose [rad]
• Ring oscillator 2011 test at 25C
– -22% after irradiation 200Mrad
– -13.8% after annealing
•
6
Dose [rad]
8
10
12
x 10
Ring oscillator 2014 test at –25C
– For same sized inverter:
• -10% @200Mrad
• -35% @1Grad
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CLICpix TID / biasing effects in
PMOS
• XRay irradiation performed to 800 MRads.
 DACs use PMOS switches to control a
current mirror for each bit.
 At high rates switches irradiated while they
are ON (their control voltage is GND)
>600 mV
degrade more quickly than the ones
A
irradiated while they are OFF.
~200 mV
 Above 200MRad, damaged switches are
I
unable to let the nominal current pass
(their driving current becomes too low).
Pierpaolo Valerio, CERN
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400nm/1u
VDD
IDAC
A
out
Iout
BUT…
 All I/O interfaces and digital structures did not show any
significant degradation during irradiation, even after the
analog front-end stopped working
 The chips regained some functionality after two week of
annealing at room temperature (the total power
consuption went back to pre-rad value). Analog
performances of the measured chip were found to be
considerably degraded.
 The measurement was performed at a dose rate of ~150
krad/minute (~75 krad/minute for the first 10 Mrads).
The high dose rate could have an effect on the radiation
damage and needs to be explored
Pierpaolo Valerio, CERN
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Summary
Unexplored territory in terms of process and radiation level.
Studies done so far on one 65nm technology mainly.
Gate effects / STI effects not clearly disentangled so-far.
NMOS: shift of Vth, drive capability loss… steep increase
above 200 MRads. Still, provided one could handle
degradation, depending on application, hint that devices
might be operated to close to ~1GRad TID down to small W.
• PMOS: Strong drive loss, narrowest devices completely off
above few 100 MRads. Indication that narrowest devices will
not work at close to 1GRad.
• Effects seeing in test IC too.
•
•
•
•
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Outlook
• Still studies too preliminary and more work to be done in wellcontrolled conditions: Biasing for PMOS? Influence of
temperature? Annealing scenario?
• Then: Other damages type (Xray / neutron/ proton …
investigate if DD becomes an issue). LDR vs HDR?
• Relation to other stresses: NBTI, HCI…
• If it is confirmed that damage is unacceptable, 2 ways out:
• Other technologies (work starts on that topic, with limited
momentum so far).
• Rules for design to be established to allow intermediate dose level
to be reached and replacement strategy.
• Still to come later: SEE studies / Statistical spread after irrad /
Modelling after irrad /etc…
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BACKUP
•BACKUP
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Core NMOS radiation performance
10
0.03
ELT,148060 nm
12060 nm
24060 nm
36060 nm
48060 nm
60060 nm
100060 nm
101 m
1010 m
0.02
Leakage current
Threshold voltage shift
10
-10
Ileak [A]
Vth [V]
0.01
-9
0
-0.01
10
-11
ELT
12060nm
24060nm
36060nm
48060nm
60060nm
100060nm
101m
1010m
-0.02
-0.03
5
10


10
7
10
TID [rad]
10
8
10
9
10
-12
10
4
10
5
10
6
10
7
10
8
10
TID [rad]
Up to ~20mV shift for 200 Mrad

Some rebound effect visible for narrow devices

in 130nm: was 150mV


At high doses Vth shift is positive for wide
devices, negative for narrow devices


6
STI edge oxide traps considerable charge (RINCE)
Subtreshold slope does not change significantly

Less than 10× increase in leakage for wide
devices (W > 360nm)
Narrow devices have up to 2.5 orders of
magnitude increase
In 130nm:



All devices are peaking at ~100nA
Narrow devices increase leakage by 3 orders of
magnitude
Ileak is ~1nA @136 Mrad
Sandro Bonacini - PH/ESE - [email protected]
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Core PMOS: Vth shift and gm loss
110
gm,max
0.06
12060 nm
24060 nm
36060 nm
48060 nm
60060 nm
100060 nm
101 m
1010 m
ELT,148060 nm
Vth [V]
0.04
0.03
100
90
gm,max normalized [%]
0.05
0.02
0.01
80
70
60
0
50
-0.01
5
10

10
7
10
TID [rad]
10
8
10
9
40
PMOS Vth shift limited to 60 mV




6
trapped charge and interface states sum up
More evident for narrow devices
Less than 10mV for transistors with W>1um
30
5
10
ELT
12060 nm
24060 nm
36060 nm
48060 nm
60060 nm
100060 nm
101 m
1010m
10
Compared to other technologies

Better performance than 130 nm




had up to 90mV @136Mrad
30mV for wide devices
7
10
TID [rad]
10
8
10
Radiation kills maximum gm,max (strong inversion)

In a 90 nm tech we observed a similar effect: 70mV @ 200Mrad
6
...but not gm in weak inversion region
Sandro Bonacini - PH/ESE - [email protected]
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