Transcript wu_20071113
Die Stacking (3D) Microarchitecture Bryan Black, Murali Annavaram, Ned Brekelbaum, John DeVale, Lei Jiang, Gabriel H. Loh1, Don McCauley, Pat Morrow, Donald W. Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Shen, and Clair Webb Intel® Corporation Micro’06 OUTLINE • • • • • • Motivation for 3D Die Stacking Manufacture Process Thermal problem Performance and Temperature Result New Circuit Design Inspiration Conclusion The Problem of Planar Floorplan 1. Faster transistors 2. Worse wire delays wire driver silicon Scaled planar circuit Planar circuit 1. D$FU : Wire Delay 1 cycle 2. RFFP : Wire Delay 2 cycle 3. Wire consumes more than 30% of the power within a microprocessor Reference: [1] Die Stacking (3D) Microarchitecture. Black, B. et al. Micro2006. [2] Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. Kiran Puttaswamy, and Gabriel H. Lohz. HPCA-13. Die-stacked 3D Integration A 4 die-stacked 3D IC silicon1 vertical interconnect driver Die 3 Die 2 Die 1 silicon0 A 2 die-stacked 3D integration Reference: [1] Die Stacking (3D) Microarchitecture. Black, B. et al. Micro2006. [2] Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. Kiran Puttaswamy, and Gabriel H. Lohz. HPCA-13. Die 0 Form Factor: One of the hottest motivation to develop 3D ICs Reference: [5] YOLE Developpement Corp. Market trends for 3D stacking Current Technology Reference: [5] YOLE Developpement Corp. Market trends for 3D stacking Comparison Reference: [5] YOLE Developpement Corp. Market trends for 3D stacking A 3D Structure D2D vias (TSV) have size and electrical characteristics similar to conventional vias that connect on die metal routing layers Face-to-Face Bounding TSV Reference: [1] Die Stacking (3D) Microarchitecture. Black, B. et al. Micro2006. [2] Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. Kiran Puttaswamy, and Gabriel H. Lohz. HPCA-13. Manufacture 1. Manufacture each die separately - start with two processed wafers Reference: [2] Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. Kiran Puttaswamy, and Gabriel H. Lohz. HPCA-13. Manufacture 2. Deposit D2D vias - Similar to building conventional vias between different metal layers, deposit copper via stubs that connect to the toplevel metal. Reference: [2] Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. Kiran Puttaswamy, and Gabriel H. Lohz. HPCA-13. Manufacture 3. Themocompression bonding - The bonding time, amount of pressure, and temperature affect the quality of the bond between the two halves of the d2d via stubs. The pressure and temperature effectively cause the two ends of the copper stubs to fuse together. Reference: [2] Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. Kiran Puttaswamy, and Gabriel H. Lohz. HPCA-13. Manufacture 4. CMP thinning - Use chemical-mechanical polishing (CMP) to thin one layer of the 3D stack to only 10 to 20 mm. Reference: [2] Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. Kiran Puttaswamy, and Gabriel H. Lohz. HPCA-13. Manufacture 5. Backside etching for power, ground and I/O - The thinning allows the backside or through-silicon vias (TSVs) that implement the external I/O and power/ground connections to be relatively short. Reference: [2] Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. Kiran Puttaswamy, and Gabriel H. Lohz. HPCA-13. Manufacture 6. Packaging(heat spreader and heat sink) Reference: [2] Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. Kiran Puttaswamy, and Gabriel H. Lohz. HPCA-13. Thermal Problems 1. Die stacking can dramatically increase power density if two highly active regions are stacked on top of each other. 2. Heat dissipation is also challenged by the fact that each additional die is stacked farther and father from the interface to the heat sink. Solution: 1. Don’t stack two highly active regions 2. The highest power die is placed closest to the heat sink. Reference: [1] Die Stacking (3D) Microarchitecture. Black, B. et al. Micro2006. [2] Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. Kiran Puttaswamy, and Gabriel H. Lohz. HPCA-13. Example Intel Pentium 4 microprocessor D$FU : Wire Delay 1 cycle RFFP : Wire Delay 2 cycle Most active unit : FP Planar floorplan 3D floorplan Reference: [1] Die Stacking (3D) Microarchitecture. Black, B. et al. Micro2006. Result - Performance Gain 1. 25% pipeline stages are eliminated. 2. 15% performance improvement. 3. 50% repeated and repeating latch is reduced. 4. The 3D grid has 50% less metal RC because the floorplan is 50% smaller 5. Fewer repeaters, a smaller clock grid, and less global wire 15% power reduction overall. Reference: [1] Die Stacking (3D) Microarchitecture. Black, B. et al. Micro2006. Result - Temperature Reference: [1] Die Stacking (3D) Microarchitecture. Black, B. et al. Micro2006. Result - Frequency and Voltage Scaling 1. To keep the same performance, we can reduce 18% voltage and yield 46% power reduction. 2. To use the same power, we can get 29% performance gain . Reference: [1] Die Stacking (3D) Microarchitecture. Black, B. et al. Micro2006. New Circuit Design Inspiration for 3D Die-Stacking Thermal Herding 1. Many data do not need full width to represent values 63:48 47:32 31:16 15:0 A 64-bit data 2. Most instruction data-widths do not vary during program execution R1 63:4847:323116 15:0 63:4847:3231:1615:0 R2 63:4847:3231:1615:0 R3 = R1 + R2 Reference: [2] Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. Kiran Puttaswamy, and Gabriel H. Lohz. HPCA-13. R3 Thermal herding 1. Significance partitioning Lower order bits of datapath (often, most switching) stay closest to the heat sink Least significant 16 bits (15:0) 2. Data-width prediction Predict data widths and disable access to higher order bits, when they are unused A 64-bit data 16 bits (31:16) 63……………………………..0 16 bits (47:32) 16 bits (63:48) Reference: [2] Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. Kiran Puttaswamy, and Gabriel H. Lohz. HPCA-13. Thermal Herding Adder Prefix-tree based planar Adder Thermal Herding 3D Adder Reference: [2] Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors. Kiran Puttaswamy, and Gabriel H. Lohz. HPCA-13. Conclusion 1. 3D die stacking increases transistor density by vertically integrating two or more die with a dense, high-seed interface. 2. Blocks within a microprocessor can be placed on different die to reduce block-to-block distance, latency, and power. 3. Disparate Si technologies can also be combined in a 3D die stack, such as DRAM stacked on a CPU. 4. Hot blocks can be folded across two strata to reduce power consumption while maintaining latency and power. 5. New circuit design tools need to be considered. Reference 1. Black, B., Annavaram, M., Brekelbaum, N., DeVale, J., Jiang, L., Loh, G. H., McCaule, D., Morrow, P., Nelson, D. W., Pantuso, D., Reed, P., Rupley, J., Shankar, S., Shen, J., and Webb, C. 2006. Die Stacking (3D) Microarchitecture. In Proceedings of the 39th Annual IEEE/ACM international Symposium on Microarchitecture 2. Rao Tummala, 2005, The SOP Technology for Convergent The SOP Technology for Convergent Electronic & Bio Electronic & Bio-electronic Systems electronic Systems. In First International Workshop on SOP, SIP, SOP Electronics Technologies. 3. Kiran Puttaswamy, and Gabriel H. Lohz. Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in HighPerformance 3D-Integrated Processors. 2007, In HPCA-13 4. Loh, G. H., Xie, Y., and Black, B. 2007. Processor Design in 3D DieStacking Technologies. IEEE Micro 27, 3 (May. 2007), 31-48. 5. YOLE Developpement Corp. Market trends for 3D stacking. Backup Page Example Intel Core 2 Dual microprocessor 1. Reduce the bandwith requirement by 3X 2. Reduce CMPA by 13% 3. Reduce bus power by 0.5W Memory stacked option Reference: [1] Die Stacking (3D) Microarchitecture. Black, B. et al. Micro2006. Example Intel Core 2 Dual microprocessor 1. The thermal impact of stacking memory is not significant Reference: [1] Die Stacking (3D) Microarchitecture. Black, B. et al. Micro2006. 3D: Stacking of Bare Chips Reference: 2] The SOP Technology for Convergent The SOP Technology for Convergent Electronic & Bio Electronic & Bio-electronic Systems electronic Systems. Rao Tummala, SSET-1