Transcript Presentation - UMass Amherst

Si and Ge NW FETs, NiSi-Si-NiSI
conductor hetero-structures and
manufacturing steps
Csaba Andras Moritz
Associate Professor
University of Massachusetts, Amherst
[email protected]
From Nanodevices to Nano
Computing
Carbon Nanotubes
(CNT)
Transistors or Diodes
Nanoarray
Nanocircuit
Lauhon et al., Nature 420,57
Semiconductor
Nanowires (NW)
Nanocomputing
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Nanowires
From Lieber, Nanoscience: Building a Big Future
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Nanowires
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Nanowire Materials
From Lieber, Nanoscience: Building a Big Future
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Comparison of NWs and CNTs
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Controlled doping of CNTs is not possible
Specific growth of semiconducting and conducting tubes
is not possible
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These properties depend sensitively on diameter and helicity in
CNTs
Semiconductor NWs overcome these limitations
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Vast knowledge in the semiconductor industry
Remain semiconducting independent on diameter
Controlled doping demonstrated, e.g., with Boron for p-type and
Phosphorus for n-type for SiNWs
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Change the conductivity of SiNWs over many orders of magnitude
Measured with Transmission Electron Microscopy (TEM)
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P and N-type SiNW (FETs)
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Yi Cui et al, The Journal of Physical Chemistry, 2000
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Electron charging
Yi Cui et al, 2000
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Specializing NWs
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Control of
composition,
structure, size,
doping
Diameter
controlled during
growth
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As small as 3nm
Stable electronic
characteristics
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FETs
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PFETs and NFETs in SiNWs, GaNi NWs
Both PFETs and NFETs in same material with Si and Ge
NWs and CNTs
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Greytak et al, American Institute for Physics, 2004
IBM Nanoscience Group lead by Davouris demonstrated CNTs
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Ge based complementary FETs
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Complementary doping demonstrated in Si,
GaN, and now Ge
 Has
been used to assemble inverters, bipolar
transistors and light emitting diodes
 Achieving p-FET and n-FET in same material was
challenging

Ge has higher electron and hole mobility than Si
and both P and N type devices have been
demonstrated
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Synthesis of p and n-type Ge NWs
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Core-shell method, doping with PH3 for N and B2H6
for P
From Greytak et al, 2004
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P and N-type Ge FETs
From Greytak et al, 2004
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Ge NWs with
Ti S-D
contacts
Vd – drainsource bias
voltage, Id the
current
through the
channel,Vggate voltage
Curves
characteristic
of MOS FETs
Yield 86%
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Comparison with Si and GaN FETs
Higher on currents than in those devices
 Higher mobilities and smaller Vth possible
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 Deposition
of Ge oxynitride or SiGe capping
layer
 Optimization of the doping procedure
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Nanoarrays
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Nanowires are
aligned with
LongmuirBlodgett fluidic
alignment
Can be
packed into
NW arrays
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Nanoarrays
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Metal/semiconductor nanowire
heterostructures
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MW-NW contacts
 Lithographically
defined metal contacts with
electrodes
 Problem: size scale – much larger than nanoscale
 Cannot be used for interconnect between FETS on a
grid
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Integrated interconnect and contact solution
based on selective transformation of Si NWs into
NiSi nanowires
 Yue
Wu et al, Nature 2004.
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Why NiSi?
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Has been shown to have low resistivity (10 uOhmcm)
Compatibility with Si manufacturing
FET with NiSi/p-Si/NiSi junction
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Si channel of 20-nm in a 10-nm diameter structure
Ability to form ohmic contacts with p and n type silicon
High maximum currents – 29-nm NiSi-NW would carry
1.84 mA
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Current density comparable to CNTs
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NiSi/Si Nanowire Heterostructures
。
Deposit
React
Etch
Si NWs
toatremove
Ni
550
(green)
C to
formexcess
to
NiSi
NWNW
(blue)
Ni(brown)
Form
Selectively
Lithography
NiSi segments
deposit
mask Ni
Form
NWs NiSi
as masks
segments
on Si NWs
Wu et al., Nature Vol. 430, pp. 61, 2004
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Modulation doped NWs for
decoders
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Very large scale integration
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Nanowires assembled
to form structures of
1,000 to 30,000
Assembled and
interconnected
> 80% yield
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Our approach:
Nano circuits based on nanoarrays
and FETs
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Why not use 2-terminal devices?
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There are several approaches resembling PLA and cell-based
FPGA like nanoFabrics, nanoPLA, CMOL
We are interested in building processor datapaths
Need for latching etc
Much higher density can be achieved even in 2-D fabrics
Even in 2-terminal arrays there is a need for signal
restoration based on FETs (see nanoPLA)
We want to know what the benefits would be and what
the challenges are from an architects point-of-view
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Manufacturing steps for large scale
2-D computing with NW FETs
(NASICs)
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Combination of self-assembly and nano lithography
Self-assembly
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Form NW array with correct doping of wires
Initial metallization between crosspoints using one set of wires as the mask
Create channel regions for FETs at cross-points
Nanolitography and conventional lithography
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Additional specialization of crosspoints with NiSi metallization
Sub 10-nm imprint lithography
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Micro-nano interfacing
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Stephen Chou et al, University of Minnesota, 1997
Not based on modification of chemical structure by radiation, its resolution is immune to many factors
that limit the resolution of conventional lithography, such as wave diffraction, scattering and
interference in resist, and the chemistry of the resist and developer
selective chemical modification (Zhong et al Science 2003)
Several other proposals (coded NWs radial doping, Distributed pin array, etc)
CMOS support structures
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