Transcript EECC722 - Shaaban

Simultaneous Multithreading (SMT)
• An evolutionary processor architecture originally
introduced in 1995 by Dean Tullsen at the University
of Washington that aims at reducing resource waste in
wide issue processors.
• SMT has the potential of greatly enhancing
superscalar processor computational capabilities by:
– Exploiting thread-level parallelism (TLP), simultaneously
issuing, executing and retiring instructions from different
threads during the same cycle.
– Providing multiple hardware contexts, hardware thread
scheduling and context switching capability.
– Providing effective long latency hiding.
EECC722 - Shaaban
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SMT Issues
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SMT CPU performance gain potential.
Modifications to Superscalar CPU architecture necessary to support SMT.
SMT performance evaluation vs. Fine-grain multithreading, Superscalar,
Chip Multiprocessors.
Ref. Papers
Hardware techniques to improve SMT performance:
SMT-1, SMT-2
– Optimal level one cache configuration for SMT.
– SMT thread instruction fetch, issue policies.
– Instruction recycling (reuse) of decoded instructions.
Software techniques:
– Compiler optimizations for SMT.
– Software-directed register deallocation.
– Operating system behavior and optimization.
SMT support for fine-grain synchronization.
SMT as a viable architecture for network processors.
Current SMT implementation: Intel’s Hyper-Threading (2-way SMT)
Microarchitecture and performance in compute-intensive workloads.
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Microprocessor Architecture Trends
CISC Machines
instructions take variable times to complete
RISC Machines (microcode)
simple instructions, optimized for speed
RISC Machines (pipelined)
same individual instruction latency
greater throughput through instruction "overlap"
Superscalar Processors
multiple instructions executing simultaneously
CMPs
Multithreaded Processors
VLIW
additional HW resources (regs, PC, SP) "Superinstructions" grouped together
each context gets processor for x cycles decreased HW control complexity
SIMULTANEOUS MULTITHREADING
multiple HW contexts (regs, PC, SP)
each cycle, any context may execute
Single Chip Multiprocessors
duplicate entire processors
(tech soon due to Moore's Law)
SMT
SMT/CMPs
EECC722 - Shaaban
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Evolution of Microprocessors
Multi-cycle
Pipelined
(single issue)
Multiple Issue (CPI <1)
Superscalar/VLIW/SMT
1 GHz
to ???? GHz
IPC
Source: John P. Chen, Intel Labs
Single-issue Processor = Scalar Processor
Instructions Per Cycle (IPC) = 1/CPI
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Microprocessor Frequency Trend
100
Intel
Processor freq
scales by 2X per
generation
IBM Power PC
DEC
Gate delays/clock
21264S
1,000
Mhz
21164A
21264
Pentium(R)
21064A
21164
II
21066
MPC750
604
604+
10
Pentium Pro
601, 603 (R)
Pentium(R)
100
486
386
2005
2003
2001
1999
1997
1995
1993
1991
1989
1
1987
10
 Frequency doubles each generation
 Number of gates/clock reduce by 25%
 Leads to deeper pipelines with more stages
Gate Delays/ Clock
10,000
Realty Check:
Clock frequency scaling
is slowing down!
(Did silicone finally hit
the wall?)
Why?
1- Power leakage
2- Clock distribution
delays
Result:
Deeper Pipelines
Longer stalls
Higher CPI
(lowers effective
performance
per cycle)
(e.g Intel Pentium 4E has 30+ pipeline stages)
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Parallelism in Microprocessor VLSI Generations
Bit-level parallelism
Instruction-level
Thread-level (?)
100,000,000
Multiple micro-operations
per cycle
(Superscalar)
Simultaneous
Multithreading SMT:
e.g. Intel’s Hyper-threading
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10,000,000
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1,000,000
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R10000
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Chip-Multiprocessors (CMPs)
e.g IBM Power 4
Pentium
Transistors

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 i80386

Chip-Level
Parallel
Processing


i80286 
100,000


 R3000
 R2000

Thread Level
Parallelism (TLP)
 i8086
10,000
 i8080
 i8008

 i4004
1,000
1970
1975
1980
1985
1990
1995
2000
2005
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CPU Architecture Evolution:
Single Threaded/Issue Pipeline
• Traditional 5-stage integer pipeline.
• Increases Throughput: Ideal CPI = 1
Register File
Fetch
Decode
Execute
Memory
Writeback
PC
SP
Memory Hierarchy (Management)
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CPU Architecture Evolution:
Superscalar Architectures
• Fetch, issue, execute, etc. more than one instruction per
cycle (CPI < 1).
• Limited by instruction-level parallelism (ILP).
Decode i
Execute i
Memory i
Writeback i
Fetch i+1
Decode i+1
Execute i+1
Memory i+1
Writeback
i+1
Fetch i
Decode i
Execute i
Memory i
Writeback i
PC
SP
Memory Hierarchy (Management)
Register File
Fetch i
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Superscalar Architectures:
Issue Slot Waste Classification
•
Empty or wasted issue slots can be defined as either vertical waste or
horizontal waste:
– Vertical waste is introduced when the processor issues no instructions in
a cycle.
– Horizontal waste occurs when not all issue slots can be filled in a cycle.
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Sources of Unused Issue Cycles in an 8-issue Superscalar Processor.
Single-Threaded
Average 1.5
instructions/cycle
issue rate
Processor busy represents the utilized issue slots; all
others represent wasted issue slots.
61% of the wasted cycles are vertical waste, the
remainder are horizontal waste.
Workload: SPEC92 benchmark suite.
SMT-1
Source: Simultaneous Multithreading: Maximizing On-Chip Parallelism Dean Tullsen et al.,
Proceedings of the 22rd Annual International Symposium on Computer Architecture, June 1995, pages 392-403.
EECC722 - Shaaban
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Single-Threaded Superscalar Architectures:
All possible causes of wasted issue slots, and latency-hiding or latency reducing
traditional techniques that can reduce the number of cycles wasted by each
cause.
SMT-1
Source: Simultaneous Multithreading: Maximizing On-Chip Parallelism Dean Tullsen et al.,
Proceedings of the 22rd Annual International Symposium on Computer Architecture, June 1995, pages 392-403.
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Advanced CPU Architectures:
Fine-grain or Traditional
Multithreaded Processors
• Multiple HW contexts (PC, SP, and registers).
• Only one context or thread issues instructions
each cycle.
• Performance limited by Instruction-Level
Parallelism (ILP) within each individual thread:
– Can reduce some of the vertical issue slot waste.
– No reduction in horizontal issue slot waste.
• Example Architecture: The Tera Computer System
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Fine-grain or Traditional Multithreaded Processors
The Tera Computer System
• The Tera computer system is a shared memory multiprocessor
that can accommodate up to 256 processors.
• Each Tera processor is fine-grain multithreaded:
– Each processor can issue one 3-operation Long Instruction Word (LIW)
every 3 ns cycle (333MHz) from among as many as 128 distinct instruction
streams (hardware threads), thereby hiding up to 128 cycles (384 ns) of
memory latency.
– In addition, each stream can issue as many as eight memory references
without waiting for earlier ones to finish, further augmenting the memory
latency tolerance of the processor.
– A stream implements a load/store architecture with three addressing
modes and 31 general-purpose 64-bit registers.
– The instructions are 64 bits wide and can contain three operations: a
memory reference operation (M-unit operation or simply M-op for short),
an arithmetic or logical operation (A-op), and a branch or simple
arithmetic or logical operation (C-op).
EECC722 - Shaaban
Source: http://www.cscs.westminster.ac.uk/~seamang/PAR/tera_overview.html
#13 Lec # 2 Fall 2005 9-5-2005
Advanced CPU Architectures:
VLIW: Intel/HP IA-64
Explicitly Parallel Instruction Computing
(EPIC)
• Strengths:
– Allows for a high level of instruction parallelism (ILP).
– Takes a lot of the dependency analysis out of HW and places
focus on smart compilers.
• Weakness:
–
–
–
–
Limited by instruction-level parallelism (ILP) in a single thread.
Keeping Functional Units (FUs) busy (control hazards).
Static FUs Scheduling limits performance gains.
Resulting overall performance heavily depends on compiler
performance.
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Advanced CPU Architectures:
Single Chip Multiprocessor
• Strengths:
– Create a single processor block and duplicate.
– Exploits Thread-Level Parallelism.
– Takes a lot of the dependency analysis out of HW and
places focus on smart compilers.
• Weakness:
– Performance within each processor still limited by
individual thread performance (ILP).
– High power requirements using current VLSI processes.
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Advanced CPU Architectures:
Single Chip Multiprocessor
Register File i
PC i
Control
Unit
i
Superscalar (Two-way) Pipeline
i
Control
Unit
i+1
Superscalar (Two-way) Pipeline
i+1
Control
Unit
n
Superscalar (Two-way) Pipeline
n
SP i
PC i+1
SP i+1
Register File n
PC n
SP n
Memory Hierarchy (Management)
Regist er File i+1
EECC722 - Shaaban
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SMT: Simultaneous Multithreading
• Multiple Hardware Contexts running at the same time (HW
context: registers, PC, and SP etc.).
• Reduces both horizontal and vertical waste by having multiple
threads keeping functional units busy during every cycle.
• Builds on top of current time-proven advancements in CPU
design: superscalar, dynamic scheduling, hardware
speculation, dynamic HW branch prediction, multiple levels of
cache, hardware pre-fetching etc.
• Enabling Technology: VLSI logic density in the order of
hundreds of millions of transistors/Chip.
– Potential performance gain is much greater than the
increase in chip area and power consumption needed to
support SMT.
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SMT
• With multiple threads running penalties from long-latency
operations, cache misses, and branch mispredictions will be
hidden:
– Reduction of both horizontal and vertical waste and thus
improved Instructions Issued Per Cycle (IPC) rate.
• Functional units are shared among all contexts during every
cycle:
– More complicated register read and writeback stages.
• More threads issuing to functional units results in higher
resource utilization.
• CPU resources may have to resized to accommodate the
additional demands of the multiple threads running.
– (e.g cache, TLBs, branch prediction tables, rename registers)
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SMT: Simultaneous Multithreading
Register File i
Superscalar (Two-way) Pipeline
i
PC i
SP i
SP i+1
Superscalar (Two-way) Pipeline
i+1
Register File n
PC n
Memory Hierarchy (Management)
PC i+1
Control Unit (Chip-Wide)
Regist er File i+1
Superscalar (Two-way) Pipeline
n
SP n
EECC722 - Shaaban
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Time (processor cycles)
The Power Of SMT
1
1
1
1
1
1 1
1
1
1
2
2
2 2
3
3 3
3 3
4
4
2 2
4
5 5
4
5
1 1
1
1
1
2
2
2
3
1
2
4
1
2
5
1
1
1
1
2 2
3
1
4 4
4
Superscalar
Traditional
Multithreaded
1 2
5
1
Simultaneous
Multithreading
Rows of squares represent instruction issue slots
Box with number x: instruction issued from thread x
Empty box: slot is wasted
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SMT Performance Example
Inst
A
B
C
D
E
F
G
H
I
J
K
•
•
•
•
•
Code
LUI
FMUL
ADD
MUL
LW
ADD
NOT
FADD
XOR
SUBI
SW
R5,100
F1,F2,F3
R4,R4,8
R3,R4,R5
R6,R4
R1,R2,R3
R7,R7
F4,F1,F2
R8,R1,R7
R2,R1,4
ADDR,R2
Description
R5 = 100
F1 = F2 x F3
R4 = R4 + 8
R3 = R4 x R5
R6 = (R4)
R1 = R2 + R3
R7 = !R7
F4=F1 + F2
R8 = R1 XOR R7
R2 = R1 – 4
(ADDR) = R2
Functional unit
Int ALU
FP ALU
Int ALU
Int mul/div
Memory port
Int ALU
Int ALU
FP ALU
Int ALU
Int ALU
Memory port
4 integer ALUs (1 cycle latency)
1 integer multiplier/divider (3 cycle latency)
3 memory ports (2 cycle latency, assume cache hit)
2 FP ALUs (5 cycle latency)
Assume all functional units are fully-pipelined
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SMT Performance Example
(continued)
Cycle
1
2
3
4
5
6
7
8
9
Superscalar Issuing Slots
1
2
3
LUI (A)
FMUL (B) ADD (C)
MUL (D)
LW (E)
ADD (F)
NOT (G)
FADD (H) XOR (I)
SW (K)
•
•
SUBI (J)
4
SMT Issuing Slots
1
2
T1.LUI (A)
T1.FMUL
(B)
T1.MUL (D)
T1.LW (E)
T2.MUL (D)
T2.LW (E)
T1.ADD (F)
T1.FADD (H)
T1.SW (K)
T2.XOR (I)
T2.SW (K)
T1.NOT (G)
T1.XOR (I)
T2.NOT (G)
T2.SUBI (J)
3
T1.ADD (C)
4
T2.LUI (A)
T2.FMUL (B)
T2.ADD (C)
T1.SUBI (J)
T2.FADD (H)
T2.ADD (F)
2 additional cycles for SMT to complete program 2
Throughput:
– Superscalar: 11 inst/7 cycles = 1.57 IPC
– SMT: 22 inst/9 cycles = 2.44 IPC
– SMT is 2.44/1.57 = 1.55 times faster than superscalar for
this example
EECC722 - Shaaban
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Modifications to Superscalar CPUs
Necessary to support SMT
•
Multiple program counters and some mechanism by which one fetch unit
selects one each cycle (thread instruction fetch policy).
•
A separate return stack for each thread for predicting subroutine return
destinations.
•
Per-thread instruction retirement, instruction queue flush, and trap
mechanisms.
•
A thread id with each branch target buffer entry to avoid predicting phantom
branches.
•
A larger register file, to support logical registers for all threads plus additional
registers for register renaming. (may require additional pipeline stages).
•
•
A higher available main memory fetch bandwidth may be required.
Larger data TLB with more entries to compensate for increased virtual to
physical address translations.
•
Improved cache to offset the cache performance degradation due to cache
sharing among the threads and the resulting reduced locality.
SMT-2
– e.g Private per-thread vs. shared L1 cache.
EECC722 - Shaaban
Source: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor,
Dean Tullsen et al. Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996, pages 191-202.
#23 Lec # 2 Fall 2005 9-5-2005
Current Implementations of SMT
• Intel’s recent implementation of Hyper-Threading
(HT) Technology (2-thread SMT) in its current P4
processor family.
• IBM POWER 5: Dual cores each 2-thread SMT.
• The Alpha EV8 (4-thread SMT) originally
scheduled for production in 2001 is currently on
indefinite hold :(
• A number of special-purpose processors targeted
towards network processor (NP) applications.
• Current technology has the potential for 4-8
simultaneous threads:
– Based on transistor count and design complexity.
EECC722 - Shaaban
#24 Lec # 2 Fall 2005 9-5-2005
A Base SMT Hardware Architecture.
SMT-2
Source: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor,
Dean Tullsen et al. Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996, pages 191-202.
EECC722 - Shaaban
#25 Lec # 2 Fall 2005 9-5-2005
Example SMT Vs. Superscalar Pipeline
Based on the Alpha 21164
Two extra pipeline stages added for reg. Read/write to account for the size increase of the register file
•
The pipeline of (a) a conventional superscalar processor and (b) that pipeline
modified for an SMT processor, along with some implications of those pipelines.
Source: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor,
SMT-2
Dean Tullsen et al. Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996, pages 191-202.
EECC722 - Shaaban
#26 Lec # 2 Fall 2005 9-5-2005
Intel Hyper-Threaded (2-way SMT) P4
Processor Pipeline
SMT-8
Source: Intel Technology Journal , Volume 6, Number 1, February 2002.
EECC722 - Shaaban
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Intel P4 Out-of-order Execution Engine
Detailed Pipeline
Hyper-Threaded (2-way SMT)
SMT-8
Source: Intel Technology Journal , Volume 6, Number 1, February 2002.
EECC722 - Shaaban
#28 Lec # 2 Fall 2005 9-5-2005
SMT Performance Comparison
•
Instruction throughput from simulations by Eggers et al. at The University
of Washington, using both multiprogramming and parallel workloads:
Multiprogramming workload
Superscalar
Threads
1
2
4
8
2.7
-
Traditional
Multithreading
2.6
3.3
3.6
2.8
SMT
3.1
3.5
5.7
6.2
Parallel Workload
Superscalar
Threads
1
2
4
8
3.3
-
MP2
MP4
2.4
4.3
-
1.5
2.6
4.2
-
Traditional
Multithreading
3.3
4.1
4.2
3.5
SMT
3.3
4.7
5.6
6.1
EECC722 - Shaaban
#29 Lec # 2 Fall 2005 9-5-2005
Possible Machine Models for an 8-way Multithreaded Processor
•
•
•
•
The following machine models for a multithreaded CPU that can issue 8 instruction per cycle
differ in how threads use issue slots and functional units:
Fine-Grain Multithreading:
– Only one thread issues instructions each cycle, but it can use the entire issue width of the
processor. This hides all sources of vertical waste, but does not hide horizontal waste.
SM:Full Simultaneous Issue:
– This is a completely flexible simultaneous multithreaded superscalar: all eight threads
compete for each of the 8 issue slots each cycle. This is the least realistic model in terms of
hardware complexity, but provides insight into the potential for simultaneous
multithreading. The following models each represent restrictions to this scheme that
decrease hardware complexity.
SM:Single Issue,SM:Dual Issue, and SM:Four Issue:
–
–
•
These three models limit the number of instructions each thread can issue, or have active in the
scheduling window, each cycle.
For example, in a SM:Dual Issue processor, each thread can issue a maximum of 2 instructions
per cycle; therefore, a minimum of 4 threads would be required to fill the 8 issue slots in one cycle.
SM:Limited Connection.
–
–
–
Each hardware context is directly connected to exactly one of each type of functional unit.
For example, if the hardware supports eight threads and there are four integer units, each integer
unit could receive instructions from exactly two threads.
The partitioning of functional units among threads is thus less dynamic than in the other models,
but each functional unit is still shared (the critical factor in achieving high utilization).
SMT-1
Source: Simultaneous Multithreading: Maximizing On-Chip Parallelism Dean Tullsen et al.,
Proceedings of the 22rd Annual International Symposium on Computer Architecture, June 1995, pages 392-403.
EECC722 - Shaaban
#30 Lec # 2 Fall 2005 9-5-2005
Comparison of Multithreaded CPU
Models Complexity
A comparison of key hardware complexity features of the various models (H=high complexity).
The comparison takes into account:
– the number of ports needed for each register file,
– the dependence checking for a single thread to issue multiple instructions,
– the amount of forwarding logic,
– and the difficulty of scheduling issued instructions onto functional units.
SMT-1
Source: Simultaneous Multithreading: Maximizing On-Chip Parallelism Dean Tullsen et al.,
Proceedings of the 22rd Annual International Symposium on Computer Architecture, June 1995, pages 392-403.
EECC722 - Shaaban
#31 Lec # 2 Fall 2005 9-5-2005
Simultaneous Vs. Fine-Grain Multithreading Performance
IPC
Workload:
SPEC92
Instruction throughput as a function of the number of threads. (a)-(c) show the throughput by thread
priority for particular models, and (d) shows the total throughput for all threads for each of the six
machine models. The lowest segment of each bar is the contribution of the highest priority thread to the
total throughput.
SMT-1
Source: Simultaneous Multithreading: Maximizing On-Chip Parallelism Dean Tullsen et al.,
Proceedings of the 22rd Annual International Symposium on Computer Architecture, June 1995, pages 392-403.
EECC722 - Shaaban
#32 Lec # 2 Fall 2005 9-5-2005
Simultaneous Multithreading Vs. Single-Chip
Multiprocessing
•
Results for the multiprocessor MP vs. simultaneous multithreading SM comparisons.The multiprocessor always has
one functional unit of each type per processor. In most cases the SM processor has the same total number of each FU
type as the MP.
SMT-1
Source: Simultaneous Multithreading: Maximizing On-Chip Parallelism Dean Tullsen et al.,
Proceedings of the 22rd Annual International Symposium on Computer Architecture, June 1995, pages 392-403.
EECC722 - Shaaban
#33 Lec # 2 Fall 2005 9-5-2005
Impact of Level 1 Cache Sharing on SMT Performance
•
Results for the simulated cache configurations, shown relative to the
throughput (instructions per cycle) of the 64s.64p
64K data cache shared
64K instruction cache private
• The caches are specified as:
[total I cache size in KB][private or shared].[D cache size][private or shared]
For instance, 64p.64s has eight private 8 KB I caches and a shared 64 KB data
Best overall performance
of configurations considered
achieved by
64s.64s
(64K data cache shared
64K instruction cache shared)
SMT-1
Source: Simultaneous Multithreading: Maximizing On-Chip Parallelism Dean Tullsen et al.,
Proceedings of the 22rd Annual International Symposium on Computer Architecture, June 1995, pages 392-403.
EECC722 - Shaaban
#34 Lec # 2 Fall 2005 9-5-2005
The Impact of Increased Multithreading on Some Low Level
Metrics for Base SMT Architecture
SMT-2
EECC722 - Shaaban
Source: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor,
Dean Tullsen et al. Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996, pages 191-202.
#35 Lec # 2 Fall 2005 9-5-2005
Possible SMT Thread Instruction Fetch Scheduling Policies
•
Round Robin:
– Instruction from Thread 1, then Thread 2, then Thread 3, etc.
(eg RR 1.8 : each cycle one thread fetches up to eight instructions
RR 2.4 each cycle two threads fetch up to four instructions each)
•
BR-Count:
– Give highest priority to those threads that are least likely to be on a wrong path
by by counting branch instructions that are in the decode stage, the rename
stage, and the instruction queues, favoring those with the fewest unresolved
branches.
•
MISS-Count:
– Give priority to those threads that have the fewest outstanding Data cache
misses.
•
ICount:
– Highest priority assigned to thread with the lowest number of instructions in
static portion of pipeline (decode, rename, and the instruction queues).
•
IQPOSN:
– Give lowest priority to those threads with instructions closest to the head of
either the integer or floating point instruction queues (the oldest instruction is at
the head of the queue).
SMT-2
EECC722 - Shaaban
Source: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor,
Dean Tullsen et al. Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996, pages 191-202.
#36 Lec # 2 Fall 2005 9-5-2005
Instruction Throughput For Round Robin
Instruction Fetch Scheduling
Best overall instruction throughput achieved using round robin RR.2.8
(in each cycle two threads each fetch a block of 8 instructions)
SMT-2
Workload: SPEC92
EECC722 - Shaaban
Source: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor,
Dean Tullsen et al. Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996, pages 191-202.
#37 Lec # 2 Fall 2005 9-5-2005
Instruction throughput & Thread Fetch Policy
ICOUNT.2.8
All other fetch heuristics provide speedup over round robin
Instruction Count ICOUNT.2.8 provides most improvement
5.3 instructions/cycle vs 2.5 for unmodified superscalar.
Workload: SPEC92
Source: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor,
Dean Tullsen et al. Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996, pages 191-202.
ICOUNT: Highest priority assigned to thread with the lowest number of
instructions in static portion of pipeline (decode, rename, and the instruction
queues).
SMT-2
EECC722 - Shaaban
#38 Lec # 2 Fall 2005 9-5-2005
Low-Level Metrics For
Round Robin 2.8, Icount 2.8
ICOUNT improves on the performance of Round Robin by 23%
by reducing Instruction Queue (IQ) clog by selecting a better mix
of instructions to queue
SMT-2
EECC722 - Shaaban
#39 Lec # 2 Fall 2005 9-5-2005
Possible SMT Instruction Issue Policies
• OLDEST FIRST: Issue the oldest instructions (those
deepest into the instruction queue, the default).
• OPT LAST and SPEC LAST: Issue optimistic and
speculative instructions after all others have been issued.
• BRANCH FIRST: Issue branches as early as possible in
order to identify mispredicted branches quickly.
Instruction issue bandwidth is not a bottleneck in SMT as shown above
Source: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor,
Dean Tullsen et al. Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 1996, pages 191-202.
ICOUNT.2.8 Fetch policy used for all issue policies above
SMT-2
EECC722 - Shaaban
#40 Lec # 2 Fall 2005 9-5-2005
SMT: Simultaneous Multithreading
• Strengths:
– Overcomes the limitations imposed by low single thread
instruction-level parallelism.
– Multiple threads running will hide individual control
hazards (branch mispredictions).
• Weaknesses:
– Additional stress placed on memory hierarchy Control
unit complexity.
– Sizing of resources (cache, branch prediction, TLBs etc.)
– Accessing registers (32 integer + 32 FP for each HW
context):
• Some designs devote two clock cycles for both register reads
and register writes.
EECC722 - Shaaban
#41 Lec # 2 Fall 2005 9-5-2005