Transcript 10 348 CHF - Indico

RF2TTC Review
May 2006
Diff LVPECL
BC1
Sinusoidal frequencies
40.07XX MHz
varying
0.6V pk-pk /8
or 0.6V pk-pk (CMS)
CAPACITIVE
COUPLING +
THEVENIN
TERMINATION FOR
DC LEVEL OF 1.2V
Sine2
Square
Diff
NECL
Diff LVPECL
MUX2:1
Sine2
Square
Diff
NECL
Diff LVPECL
LVDS
800mV swing
Diff
NECL
ECL
V_comp3
comparator
AD96685
BC1 NIM/OUT
PECL2NIM
PLL&
VCXO
LVDS
LVDS
FAN1:4
PECL
BC2 ECL/OUT
ECL Driver
LVDS
800mV swing
Diff LVPECL
LVDS2ECL
text
Phase
Adjust
BC2 NIM/OUT
PECL2NIM
BCref_CLOCK
LVPECL2LVDS
PLL&
VCXO
LVDS
BCref sel
LVDS
FAN1:4
PECL
BCref
ECL/OUT
ECL Driver
BCref
NIM/OUT
LVDS2ECL
Diff LVPECL
DELAY25
INTERNAL
CLOCK
V_comp4
Orb1 det
2.5V
CMOS
MAIN BC
NIM/OUT
MAIN BC
DELAY25
Fine
Delay
2.5V
CMOS
BC1 lock
BC2 lock
BCref lock
MAIN BC lock
text
2.5V
CMOS
Fine
Delay
RF2TTC BOARD
BLOCK DIAGRAM V1.7
28/04/2006
2.5V
CMOS
Orbit1
Orbit2
MAIN BC int/BC1
BC2/Bcref
MAIN ORBIT Or1/Or2/
Int
74AHC123
BCsel[1..0]
Lock, TTCready, ...
Machine Mode Run/No
INTERNAL
CNT
V_comp5
DACs
& Ref
Voltage
BC & ORBIT SOURCES
SELECTION, DACs
adjustment for Orbit
comparators
I2C interface
BOARD STATUS
D
SET
CLR
Q
Multiplexer
S1
D
Coarse
Delay
S4
C1
C2
ENB
BC1 CLOCK
Multiplexer
S1
MACHINE MODES
FINE DELAYS CONTROL
REMOTE
CONTROL
BST decoder
INTERNAL
CNT
D
SET
CLR
Coarse
Delay
ORBIT1
NIM/OUT
Adjust.
Stretch
er
ECL2NIM
BC2_clock
C1
Q
C2
ORBIT2
NECL/OUT
ENB
BC2 CLOCK
ECL Driver
Fine
text
Delay
LVDS2ECL
ECL2NIM
D
SET
STATUS REGISTERS
CLR
Q
SET
CLR
S1
INTERNAL CLOCK
C1
Q
MAIN ORBIT
NECL/OUT
D
Coarse
Delay
S4
Adjust.
Stretch
er
Q
Q
ORBIT2
NIM/OUT
Multiplexer
Sync
D
ORBIT1
NECL/OUT
ECL Driver
D
S4
Q
INTERNAL
CNT
VME INTERFACE
INTERNAL
CLOCK
Fine
Delay
LVDS2ECL
Sync
VME BUS
VME BACKPLANE
BC1_clock
VME access
VME_Berr
BST_ready
NECL
Sync
MACHINE MODES
Adjust.
Stretch
er
MC10EP89 ECL
coax cable
drivers
Q
Orbit sel
TTCrx
PECL2NIM
ECL2NIM
CONVERSION
USING BSR17A
TRANSISTORS
Orb2 det
40 ns LVPECL
Stretch
er
MAIN BC
ECL/OUT
ECL Driver
FAN1:4
MAIN BC lock
DELAY25
5ns
square
pulse
ECL
comparator
AD96685
DELAY25
Step 500ps, range 25ns
LVDS
LVDS2ECL
40 ns LVPECL
Orbit
detect
PECL
PLL&
VCXO
LVDS
MAIN BC
sel[1..0]
I2C
Orbit
detect
QPLL
Phase
Adjust
LVPECL2LVDS
Stretch
er
Sine2
Square
LVDS
800mV swing
MUX4:1
Diff LVPECL
5ns
square
pulse
Sine2
Square
PECL2NIM
FAN1:4
AC
COUPLING
Sophie BARON, PH-ESS
BC1 ECL/OUT
ECL Driver
BC2 lock
MUX2:1
AC
COUPLING
LVPECL QUARTZ
80.158MHz
BST
SIGNAL
OPTICAL
TTC
FRAMES
PECL
BCref lock
PLL&
VCXO
FROM RF OPTICAL
RECEIVERS
FAN1:4
BC2_CLOCK
LVPECL2LVDS
Diff LVPECL
ORBIT2
Phase
Adjust
BC2sel
Sine2
Square
BC ref
Sine pulse
1V peak (0-1V)
5ns width
LVDS
BC1 lock
LVDS2ECL
MUX2:1
AC
COUPLING
V_comp2
ORBIT1
PLL&
VCXO
LVDS
Diff LVPECL
v
BC2
Sinusoidal frequency
40.07XX MHz
fixed
0.6V pk-pk / 8
or 0.6V pk-pk (CMS)
Phase
Adjust
LVPECL2LVDS
BC1sel
V_comp1
BC1_CLOCK
LVDS
800mV swing
Diff LVPECL
AC
COUPLING
MC10EP89 ECL
coax cable
drivers
QPLL
C2
Fine
Delay
ECL Driver
LVDS2ECL
ENB
ECL2NIM
Orbit sel
Sync
FPGA
TTC meeting, 2nd of May 2006
MAIN ORBIT
NIM/OUT
ECL2NIM
CONVERSION
USING BSR17A
TRANSISTORS
MAIN BC CLOCK
MAIN BC
1




Sophie BARON, PH-ESS
Receiver Crate
Functionalities
Design
AOB
TTC meeting, 2nd of May 2006
2
RECEIVER CRATE [Overview]
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
3
RECEIVER CRATE [Location]
Magnetic field:
Radiations:
Total dose:
Ch Hadrons >20MeV fluency:
Neutrons>20MeV:
<100gauss
1.4 rad/10yrs
1.5 106/10yrs/cm-2
3.1 106/10yrs/cm-2
TTClab (build 4)
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
4
RECEIVER CRATE [Crates]
 ATLAS, CMS, LHCb:
o 1 LHC standard 6U VME crate per experiment
o Power supply type OP06.0710 (+3.3V/100A, +5V/100A, +-12V/10A, 48V/12A)
 ALICE:
o 1 ALICE Trigger standard 6U VME crate (water cooled)
o Power supply type changed from 0P17.0711 to 0P17.0701 (+3.3V/100A,
+5V/100A, +/-12V/10A)
 TTC lab:
o 1 LHC standard 6U VME crate per experiment
o Power supply type OP06.0710 (+3.3V/100A, +5V/100A, +-12V/10A, 48V/12A)
 RF:
o Use VME64 crates (no P3V3).
 RF2TTC and fanout modules use +3V3, +5V and +-12V
 RF_Tx and RF_Rx use only +5V and +-12V
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
5
RECEIVER CRATE [Crate Controllers]
 ALICE:
o Standard VP315/317 from CCT
 ATLAS:
o Standard VP110 from CCT
 CMS:
o CAEN PCI-controller card A2818 + V2718 VME-PCI optical bridge
 LHCb:
o CAEN V1718 VME-USB bridge
All these modules are POOL items. One of each will be reserved as from
August 06.
The TTClab is equipped with a VP110.
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
6
RECEIVER CRATE [RF Analog Links]
 Analog Modules
o Transmitter module: RF_Tx_A (EDA-01331)
o Receiver module: RF_Rx_A (EDA-01332)
 Miteq links validated
• Specs:
– Freq max: 3GHz (typ)
– Vin: 10dBm (max)
– Vout: 10dBm (max)
• Measured Phase Noise:
– 400MHz -> 0.4ps (pkpk)
– 40MHz -> 0.4ps (pkpk)
– 10MHz -> 13ps (pkpk)
More results in the evaluation report
• Typical output levels:
– Bunch Clock = 0dBm continuous sinewave
– Orbit = 1Vpk pulse on 50 Ohms
• Quantities:
– 10 links have been ordered in November05
– 10 to be ordered soon
=> Enough to work until 2007
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
7
RECEIVER CRATE [RF Analog Links]
 6U 4TE VME (VME 64x and VME 64 compatible)
o 3 internal registers
• Power warning led threshold (RW)
• CH1Power monitoring (Read Only)
• CH2 Power monitoring (Read Only)
o Manual or geographical addresses
o Emi Filters on each laser power pin
o FPGA programmed using VHDL/ Visual Elite to match the AB/RF
requirements
o Heat sink required to keep the Miteq Rx and Tx at about 35 C Deg.
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
8
RECEIVER CRATE [RF Analog Links]
 Power consumption:
+5V
+12V
-12V
Tx
0.7A
0.7A
0.2A
Rx
0.7A
0.7A
0
 Component price/ dual module
MITEQ
Others
Total
Tx
3174
178
6 527 CHF
Rx
5079
190
10 348 CHF
Sophie BARON, PH-ESS
•Some layout changes on-going
following the review done with AB/RF
•PCB manufacture to begin this
week
TTC meeting, 2nd of May 2006
9
RECEIVER CRATE [RF Digital Links]
 Digital Modules (RF_Tx_D and RF_Rx_D)
o First test boards made with PHOTON 155Mbps/TRR-1B43 pair
• Performance evaluated on the same setup than the analog links
• Results available in the test report
• AB/RF agreed that this could be a cheaper solution for 70% of the links, including
the TTC
• If the final results are as good as expected, they will use this solution for these 70%
and maintain the boards the same way.
o Optical components identified and ordered
• Photon getting obsolete
• AMS components pin compatible components
• Price:
– Orbit, 10MHz, 40MHz: 156Mbps links
– 400MHz: 1.2Gbps
o Design on-going (PH/ESS).
Tx
Rx
156Mbps PHOTON
197
97
156Mbps AMS
313
227
1.2Gbps AMS
635
295
• Close to the analog boards, but higher density.
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
10
RECEIVER CRATE [Client modules]
Standard TTC modules:
Coupling
Termination
BC in
AC
50 to vbb
A in
DC
NECL120/82 (=-2.1VDC)
B in
DC
NECL120/82 (=-2.1VDC)
BC out
AC
120/82 (=-2.1VDC)
L1a_in
AC
240/62 (=-1.1VDC)
BC_in
AC
240/62 (=-1.1VDC)
Orbit_in
AC
240/62 (=-1.1VDC)
ECL_out
DC
NECL 560 to -5V2
BC in
AC
240/62 (=-1.1VDC)
A_in
DC
NECL120/82 (=-2.1VDC)
B_in
DC
NECL120/82 (=-2.1VDC)
BC_in
AC
120/82 (=-2.1VDC)
BC_out
AC
120/82 (=-2.1VDC)
Sig_in
AC
120/82 (=-2.1VDC)
Sig_out
AC
150 to GND (PECL)
TTCex
Custom modules:
o ATLAS CTP
o TTCci
o ..
TTCvi
TTCvx
TTCClkGen
TTCFanout
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
To have a full compatibility with
all the client modules,
•The BC_out signals can be
ECL AC coupled
•The Orbit_out signals need to
be NECL DC coupled
11
RECEIVER CRATE [TTC Clock fanout]
 TTC Clock fanout (EDA-01240-V1, PH/MIC)
o
o
o
o
o
o
Dual 1:18 ECL fanout
4 NIM outputs per input (ALICE requirement)
1 status led per input (presence of clock).
Maximum density
The 2 dual modules can be daisy chained.
Fully AC coupled
Prototype produced



Power: 5V-5A,
Jitter: In/Out skew=8ps rms, Cy2Cy=11ps rms
Skew between outputs: a few ps
Design needs to be adjusted to be ‘orbit-compliant’ (AC -> DC coupling)
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
12




Sophie BARON, PH-ESS
Receiver Crate
Functionalities
Design
AOB
TTC meeting, 2nd of May 2006
13
FUNCTIONALITIES [Inputs/Outputs]
RF2TTC
VME
BC1 lock
BC2 lock
BCref lock
Orbit1
Orbit2
1 2 Ref Int
BC
Orb
LHC Mode
BST
BC INPUTS
BC ring1
BC ring2
BC REF
ORBIT INPUTS
 VME 6U module
 1 slot if possible
 Inputs
o 3 BC inputs (SMA or Lemo00) (RF signals)
o 2 Orbit inputs (RF signals)
o 1 Optical input for the BST signals
 Outputs (can be discussed)
Orb ring1
Orb ring2
o 4 ECL BC outputs (BC1, BC2, BCref, MainBC)
• AC coupled
BC OUTPUTS
BC1/ecl BC1/nim
BC2/ecl BC2/nim
BC/ecl
BC/nim
MAIN
BC/ecl BC/nim
o 4 NIM copies
o 3 NECL Orbit outputs (Orb1, Orb2, MainOrb)
• DC coupled
• Synchronised respectively to BC1, BC2, MainBC
ORBIT OUTPUTS
Or1/ecl Or1/nim
Or2/ecl Or2/nim
MAIN
Or2/ecl Or2/nim
o 3 NIM copies
 Status leds
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
14
FUNCTIONALITIES [Block Diagram]
Diff LVPECL
BC1
Sinusoidal frequencies
40.07XX MHz
varying
0.6V pk-pk /8
or 0.6V pk-pk (CMS)
CAPACITIVE
COUPLING +
THEVENIN
TERMINATION FOR
DC LEVEL OF 1.2V
Sine2
Square
Diff
NECL
Diff LVPECL
MUX2:1
Sine2
Square
Diff
NECL
LVDS
800mV swing
Diff
NECL
ECL
V_comp3
comparator
AD96685
BC1 ECL/OUT
ECL Driver
BC1 NIM/OUT
PECL2NIM
BC2_CLOCK
PLL&
VCXO
LVDS
LVDS
FAN1:4
PECL
BC2 ECL/OUT
ECL Driver
BC2 lock
LVDS
800mV swing
Diff LVPECL
MUX2:1
AC
COUPLING
LVDS2ECL
text
Phase
Adjust
BC2 NIM/OUT
PECL2NIM
BCref_CLOCK
LVPECL2LVDS
PLL&
VCXO
LVDS
BCref sel
LVDS
FAN1:4
PECL
BCref
ECL/OUT
ECL Driver
BCref
NIM/OUT
LVDS2ECL
Diff LVPECL
DELAY25
INTERNAL
CLOCK
Orbit
detect
V_comp4
2.5V
CMOS
MAIN BC
NIM/OUT
MAIN BC
PECL2NIM
ECL2NIM
CONVERSION
USING BSR17A
TRANSISTORS
DELAY25
Fine
Delay
2.5V
CMOS
Adjustable
BC1 lock
BC2 lock
BCref lock
text
2.5V
CMOS
Fine
Delay
MAIN BC lock
Reset
possible
RF2TTC BOARD
BLOCK DIAGRAM V1.7
28/04/2006
2.5V
CMOS
Orbit1
Orbit2
Monitored
MAIN BC int/BC1 via a
BC2/Bcref
register
MAINVME
ORBIT Or1/Or2/
Int
74AHC123
BCsel[1..0]
Lock, TTCready, ...
Machine Mode Run/No
Status Led
INTERNAL
CNT
V_comp5
DACs
& Ref
Voltage
BC & ORBIT SOURCES
SELECTION, DACs
adjustment for Orbit
comparators
I2C interface
BOARD STATUS
D
SET
CLR
Q
Multiplexer
S1
D
Coarse
Delay
S4
C2
ENB
BC1 CLOCK
Multiplexer
S1
MACHINE MODES
INTERNAL
CNT
FINE DELAYS CONTROL
REMOTE
CONTROL
BST decoder
D
SET
CLR
LVDS2ECL
Coarse
Delay
ORBIT1
NIM/OUT
Adjust.
Stretch
er
ECL2NIM
BC2_clock
Q
C1
Q
C2
ORBIT2
NECL/OUT
ENB
BC2 CLOCK
ECL Driver
Fine
text
Delay
ECL2NIM
INTERNAL
CNT
SET
VME INTERFACE
STATUS REGISTERS
CLR
Q
SET
CLR
INTERNAL CLOCK
C1
Q
MAIN ORBIT
NECL/OUT
D
Coarse
Delay
S4
Adjust.
Stretch
er
Q
Q
ORBIT2
NIM/OUT
Multiplexer
S1
Sync
D
ORBIT1
NECL/OUT
ECL Driver
LVDS2ECL
D
INTERNAL
CLOCK
Fine
Delay
D
S4
Sync
VME BUS
VME BACKPLANE
BC1_clock
VME access
VME_Berr
BST_ready
NECL
C1
Orbit sel
TTCrx
Adjust.
Stretch
er
MC10EP89 ECL
coax cable
drivers
Q
Sync
MACHINE MODES
Sophie BARON, PH-ESS
FAN1:4
Orb2 det
40 ns LVPECL
Stretch
er
MAIN BC
ECL/OUT
ECL Driver
MAIN BC lock
DELAY25
5ns
square
pulse
ECL
comparator
AD96685
DELAY25
Step 500ps, range 25ns
LVDS
LVDS2ECL
Orb1 det
40 ns LVPECL
Stretch
er
PECL
PLL&
VCXO
LVDS
MAIN BC
sel[1..0]
I2C
Orbit
detect
QPLL
Phase
Adjust
LVPECL2LVDS
5ns
square
pulse
Sine2
Square
LVDS
800mV swing
MUX4:1
Diff LVPECL
LVPECL QUARTZ
80.158MHz
Sine2
Square
PECL2NIM
FAN1:4
AC
COUPLING
BST
SIGNAL
OPTICAL
TTC
FRAMES
PECL
BCref lock
PLL&
VCXO
FROM RF OPTICAL
RECEIVERS
Phase
Adjust
LVPECL2LVDS
Diff LVPECL
ORBIT2
FAN1:4
BC1 lock
BC2sel
Sine2
Square
BC ref
Sine pulse
1V peak (0-1V)
5ns width
LVDS
LVDS2ECL
Diff LVPECL
MUX2:1
AC
COUPLING
V_comp2
ORBIT1
PLL&
VCXO
LVDS
Diff LVPECL
v
BC2
Sinusoidal frequency
40.07XX MHz
fixed
0.6V pk-pk / 8
or 0.6V pk-pk (CMS)
Phase
Adjust
LVPECL2LVDS
BC1sel
V_comp1
BC1_CLOCK
LVDS
800mV swing
Diff LVPECL
AC
COUPLING
MC10EP89 ECL
coax cable
drivers
QPLL
C2
Fine
Delay
ECL Driver
LVDS2ECL
ENB
ECL2NIM
ECL2NIM
CONVERSION
USING BSR17A
TRANSISTORS
Orbit sel
Sync
FPGA
TTC meeting, 2nd of May 2006
MAIN ORBIT
NIM/OUT
MAIN BC CLOCK
MAIN BC
15
FUNCTIONALITIES [VME Interface]
 VME Interface
o D32/A32 access mode (AM 0x09)
o 8 bits of board address (A31-A24) (2 rotary switches).
o Geographical addresses usable if the manual address is 0x00
(reloaded at power up or by sysreset)
o Interrupts are possible, but have to remain optional. They may not be
handled by every types of VME controllers.
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
16
FUNCTIONALITIES [Signal Adjustments]
 Adjustable parameters (via VME registers)
o BC1, BC2, BCref
• Adjustable level on the comparator input
• Multiplexing between each input and the internal 40.078MHz clock
• Adjustable phase shift (steps of 0.5ns)
o Main BC
• Multiplexing between BC1, BC2, BCref and internal clock
• Adjustable phase shift (steps of 0.5ns)
o Orbit1 and Orbit2
•
•
•
•
•
•
Adjustable level on the comparator input to match various types of signals
Adjustable phase shift before the latching with the corresponding BC
Multiplexing between each input and an internal counter
Adjustable length
Adjustable coarse delay (steps of 25ns)
Adjustable phase shift (steps of 0.5ns) before the output
o Main Orbit
•
•
•
•
Multiplexing between the two orbit sources and an internal counter
Adjustable length
Adjustable coarse delay (steps of 25ns)
Adjustable phase shift (steps of 0.5ns) before the output
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
17
FUNCTIONALITIES [Status & Remote Control]
 Board status data
o Read only registers: Orbit available, QPLL lock, TTC ready, machine
mode
o Leds: selected signals, QPLL lock, available orbit, VME access, VME
berr, BST signal ready...
 Remote control of the adjustments
o Orbit comparator level/ orbit dephasing: FIFO containing the 128 last
BC counts between two consecutive Orbit signals (ideally 3564 each).
The content of this FIFO can indicate a bad level on the comparator, a
dephasing, a wrong synchronisation. This FIFO is filled at reception of
a VME command.
o Clock status: QPLL status indicates if the clock is absent or if the
comparator level is wrong. Would some other ways being required?
o Orbit counter, 32 bits (106 hours). Could be reset, either manually, or
at the beginning of a run if required
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
18
FUNCTIONALITIES [Working modes]
 Manual and automatic modes for signal selection
o Manual mode: the source of each output signal is manually selected
o Automatic mode:
• Change the selected sources according to the machine mode
• 2 types of parameters must be configured:
– Which machine mode is considered to be ‘run’ (ex: ramping, adjust, collide..) or ‘no run’
(beam dump, no beam, …)
– Which source for each signal must be selected during ‘run’ or ‘no run’. Example for the
Main BC: Internal clock during ‘no run’ periods, and BCref during run periods
• 3 different configurations can be defined for the signal selection.
o Which means:
•
•
•
•
1 register to define in which mode we are (manual, auto1, auto2, auto3)
1 register to define which machine mode corresponds to which state
1 register to define the sources set when ‘no run’…………………
3 registers to define the sources set when ‘run’ (1 per auto mode)…
Beam Dump
Beam Dump
time
injection ramping squeeze physics
~15 min ~28 min ~15 min ~10-20 H
Run/no run
Automode1
Automode2
Automode3
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
19
FUNCTIONALITIES [State Machine]
Beam Dump
Beam Dump
time
injection ramping squeeze physics
~15 min ~28 min ~15 min ~10-20 H
Run/no run
Automode1
Automode2
Automode3
Manual
MANUAL
NO RUN
[no_run]
RUN
[auto1]
RUN
[auto3]
RUN
[auto2]
AUTO MODE
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
20
FUNCTIONALITIES [register map -1]
Bunch Clocks registers
BC#
BC1_COMP_Vref
R/W
8 bits
Voltage reference to be compared to the BC1 input
BC1_QPLL_STATUS
R
2 bits
Locked, error
BC1_QPLL_MODE
R/W
1 bit
autorestart or manual restart mode
BC1_FINE_DELAY
R/W
7 bits
enable the line, and delay adjustment (steps of 0.5ps)
BC1_SOURCE_SEL
R/W
1 bit
BC source can be chosen between the internal 40.078MHz and the LHC BC1 when the selection mode is
manual
BC1_RESERVED_#
R/W
16 bits
MainBC
MainBC_QPLL_STATUS
R
Locked, error
MainBC_QPLL_MODE
R/W
1 bit
autorestart or manual restart mode
MainBC_FINE_DELAY
R/W
7 bits
enable the line, and delay adjustment (steps of 0.5ps)
MainBC_SOURCE_SEL
R/W
2 bits
MainBC source can be chosen between the internal 40.078MHz and the LHC
BC1, BC2 and BCref
MainBC_RESERVED_#
R/W
16 bits
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
21
FUNCTIONALITIES [register map -2]
Orbit registers
ORBIT#
Orb1_COMP_Vref
R/W
8 bits
set the threshold value used to latch the Orb signal
Orb1_SOURCE_SEL
R/W
1 bit
Orb1 source can be chosen between the Orb1 Internal counter and the LHC
Orb1
Orb1_DETECTED
R
1 bit
shows if the orbit signal is available
Orb1_DETECTED_PERIOD
R
12 bits
Each read access gives the last number of BCs between 2 Orbit signals stored in
a 128 words FIFO (to check the Orbit dephasing). The 4 upper bits give
the status of the fifo when the word is read (full, empty, almost full..)
Orb1_FINE_IN_DELAY
R/W
7 bits
enable the line, and delay adjustment (steps of 0.5ps) to adjust the phase of the
input signal vs the latching BC
Orb1_COARSE_DELAY
R/W
12 bits
delay adjustment of the Orbit signal in 3564 steps of 25ns (0 to 88.924us)
Orb1_WIDTH
R/W
12 bits
orbit pulse width adjustment in 3564 steps of 25ns (0 to 88.924us)
Orb1_FINE_OUT_DELAY
R/W
7 bits
enable the line, and delay adjustment (steps of 0.5ps) to adjust the phase of the
output signal vs the BC used by the experiments
Orb1_Int_PERIOD
R/W
12 bits
set the period of the internal orbit (from 0 to 102us in steps of 25ns, sync to BC1)
Orb1_Int_COUNTER
R
12 bits
Result of the Orbit1_int counter (counts the BC between 2 orbits). Reset by each
new orbit.
Orb1_COUNTER
R
32 bits
Result of the Orbit1 counter (counts the Orbit signal, up to 106 hours). Manually
reset or by the beginning of a run ? (how?)
Orb1_RESERVED_#
R/W
16 bits
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
22
FUNCTIONALITIES [register map -3]
Orbit registers
MainORBIT
MainOrb_SOURCE_SEL
R/W
2 bits
MainOrb source can be chosen between the internal MainOrb counter,
the LHC Orb1 and the LHC orb2
MainOrb_COARSE_DELAY
R/W
12 bits
delay adjustment of the Orbit signal in 3564 steps of 25ns (0 to
88.924us)
MainOrb_WIDTH
R/W
12 bits
orbit pulse width adjustment in 3564 steps of 25ns (0 to 88.924us)
MainOrb_FINE_OUT_DELAY
R/W
7 bits
enable the line, and delay adjustment (steps of 0.5ps) to adjust the
phase of the output signal vs the BC used by the experiments
MainOrb_Int_PERIOD
R/W
12 bits
set the period of the internal orbit (from 0 to 102us in steps of 25ns,
sync to MainBC)
MainOrb_Int_COUNTER
R
12 bits
Result of the MainOrbit_int counter (counts the BC between 2 orbits).
Reset by each new orbit.
32 bits
Result of the MainOrbit counter (counts the Orbit signal, up to 106
hours). Manually reset or by the beginning of a run ? (how?)
MainOrb_COUNTER
MainOrb_RESERVED_#
Sophie BARON, PH-ESS
R/W
16 bits
TTC meeting, 2nd of May 2006
23
FUNCTIONALITIES [register map -4]
BST registers
TTCrx
TTCrx_CONFIG1
R/W
TTCrx_CONFIG2
R/W
TTCrx_CONFIG3
R/W
TTCrx_STATUS
R
TTCrx_RESERVED_1
R/W
16 bits
BST MESSAGE
MACHINE_MODE
R
8 bits
BST _RESERVED_1
R/W
32 bits
Sophie BARON, PH-ESS
decode the LHC Machine Mode transmitted by the BST
TTC meeting, 2nd of May 2006
24
FUNCTIONALITIES [register map -5]
General registers
GENERAL REGISTERS
BOARD ID
R/W
8 bits
FIRMWARE VERSION
R/W
8 bits
BC_Delay25_GCTRL
R/W
8 bits
general parameters of the delay 25 chip in charge of all the BC fine delay adjustment
Orb_In_Delay25_GCTRL
R/W
8 bits
general parameters of the delay 25 chip in charge of all the Orb in fine delay adjustment
Orb_Out_Delay25_GCTRL
R/W
8 bits
general parameters of the delay 25 chip in charge of all the Orb out fine delay adjustment
Working Modes
R/W
4 bits
0: manual mode
1: automatic mode 1
2: automatic mode 2
3: automatic mode 3
Automatic_config_no_run
R/W
9 bits
Describes the state of the selection of the signals in automatic modes, out of the run
periods.
Automatic_config_run_1
R/W
9 bits
Describes the state of the selection of the signals in automatic mode 1, during the run.
Automatic_config_run_2
R/W
9 bits
Describes the state of the selection of the signals in automatic mode 2, during the run.
Automatic_config_run_3
R/W
9 bits
Describes the state of the selection of the signals in automatic mode 3, during the run.
Machine_states_config
R/W
32 bits
One bit per machine mode. Use automatic_config_0 when bit#=0, use one of the
automatic_config1 to 3 when bit#=1.
GNAL_RESERVED_1
R/W
32 bits
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
25
FUNCTIONALITIES [register map -6]
Commands
RESET
BC1_QPLL_RESET
BC2_QPLL_RESET
BCref_QPLL_RESET
MainBC_QPLL_RESET
Delay25_RESET
Orb1_counter_fifos_reset
Orb_counters_reset
BOARD_RESET
COMMANDS
Orb1_fifo_fill
trig the filling of the FIFO with the periods of 128 consecutive orbit1 signals
Orb2_fifo_fill
trig the filling of the FIFO with the periods of 128 consecutive orbit1 signals
CMD_RESERVED_#
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
26




Sophie BARON, PH-ESS
Receiver Crate
Functionalities
Design
AOB
TTC meeting, 2nd of May 2006
27
DESIGN [Block Diagram]
Sinusoidal frequencies
40.07XX MHz
varying
0.6V pk-pk /8
or 0.6V pk-pk (CMS)
CAPACITIVE
COUPLING +
THEVENIN
TERMINATION FOR
DC LEVEL OF 1.2V
Diff LVPECL
BC1
Sine2
Square
Diff
NECL
Diff LVPECL
MUX2:1
AC
COUPLING
BC1_CLOCK
Sine2
Square
Diff
NECL
LVDS
FAN1:4
PECL
BC1 ECL/OUT
ECL Driver
BC1 lock
LVDS2ECL
Diff LVPECL
MUX2:1
AC
COUPLING
LVDS
800mV swing
BC1 NIM/OUT
BC2_CLOCK
PLL&
VCXO
LVDS
BC2sel
Diff
NECL
ECL
V_comp3
comparator
AD96685
LVDS
800mV swing
Diff LVPECL
MUX2:1
AC
COUPLING
LVDS
FAN1:4
PECL
BC2 ECL/OUT
ECL Driver
BC2 lock
Diff LVPECL
Sine2
Square
BC ref
Phase
Adjust
PECL2NIM
LVPECL2LVDS
V_comp2
LVDS2ECL
text
Phase
Adjust
BC2 NIM/OUT
PECL2NIM
BCref_CLOCK
LVPECL2LVDS
PLL&
VCXO
LVDS
BCref sel
LVDS
FAN1:4
PECL
BCref
ECL/OUT
ECL Driver
BCref lock
BCref
NIM/OUT
LVDS2ECL
Diff LVPECL
DELAY25
LVDS
800mV swing
MUX4:1
Diff LVPECL
INTERNAL
CLOCK
5ns
square
pulse
PLL&
VCXO
LVDS
LVDS
LVDS
MAIN BC
ECL/OUT
ECL Driver
FAN1:4
MAIN BC
NIM/OUT
MAIN BC lock
LVDS2ECL
40 ns LVPECL
Stretch
er
PECL
DELAY25
Step 500ps, range 25ns
MAIN BC
sel[1..0]
Orb1 det
Orbit
detect
QPLL
Phase
Adjust
LVPECL2LVDS
LVPECL QUARTZ
80.158MHz
Sine2
Square
PECL2NIM
FAN1:4
AC
COUPLING
I2C
PLL&
VCXO
ORBIT1
PLL&
VCXO
LVDS
Diff LVPECL
v
BC2
Sinusoidal frequency
40.07XX MHz
fixed
0.6V pk-pk / 8
or 0.6V pk-pk (CMS)
Phase
Adjust
LVPECL2LVDS
BC1sel
V_comp1
MC10EP89 ECL
coax cable
drivers
QPLL
LVDS
800mV swing
Diff LVPECL
MAIN BC
PECL2NIM
ECL2NIM
CONVERSION
USING BSR17A
TRANSISTORS
DELAY25
Fine
Delay
CMOS
BC1 lock
BC2 lock
BCref lock
MAIN BC lock
ECL2LVDS
Sine pulse
1V peak (0-1V)
5ns width
ORBIT2
FROM RF OPTICAL
RECEIVERS
Orbit
detect
V_comp4
text
RF2TTC BOARD
BLOCK DIAGRAM V1.7
28/04/2006
DELAY25
5ns
square
pulse
Sine2
Square
Orb2 det
40 ns LVPECL
Stretch
er
LVDS
Fine
Delay
CMOS
ECL
comparator
AD96685
74AHC123
BCsel[1..0]
Lock, TTCready, ...
Machine Mode Run/No
INTERNAL
CNT
V_comp5
DACs
& Ref
Voltage
BC & ORBIT SOURCES
SELECTION, DACs
adjustment for Orbit
comparators
I2C interface
BOARD STATUS
D
SET
CLR
Q
Multiplexer
S1
D
Coarse
Delay
S4
C2
REMOTE
CONTROL
BST decoder
MACHINE MODES
INTERNAL
CNT
D
SET
CLR
BC1 CLOCK
Coarse
Delay
S4
ORBIT1
NIM/OUT
Adjust.
Stretch
er
ECL2NIM
BC2_clock
C1
Q
C2
ORBIT2
NECL/OUT
ENB
BC2 CLOCK
ECL Driver
Fine
text
Delay
ECL2NIM
D
SET
CLR
SET
Q
CLR
INTERNAL CLOCK
Coarse
Delay
S4
C1
Q
Q
MAIN ORBIT
NECL/OUT
D
Adjust.
Stretch
er
Q
Sync
FPGA
ORBIT2
NIM/OUT
Multiplexer
S1
Sync
D
ORBIT1
NECL/OUT
ECL Driver
CMOS2ECL
Q
INTERNAL
CNT
STATUS REGISTERS
Sophie BARON, PH-ESS
VME access
VME_Berr
BST_ready
CMOS2ECL
VME INTERFACE
INTERNAL
CLOCK
Fine
Delay
D
Sync
VME BUS
VME BACKPLANE
BC1_clock
ENB
Multiplexer
FINE DELAYS CONTROL
MACHINE MODES
MC10EP89 ECL
coax cable
drivers
NECL
C1
S1
TTCrx
Adjust.
Stretch
er
Q
Sync
Orbit sel
BST
SIGNAL
OPTICAL
TTC
FRAMES
Orbit1
Orbit2
MAIN BC int/BC1
BC2/Bcref
MAIN ORBIT Or1/Or2/
Int
ECL2LVDS
C2
Fine
Delay
ECL Driver
CMOS2ECL
ENB
ECL2NIM
MAIN ORBIT
NIM/OUT
ECL2NIM
CONVERSION
USING BSR17A
TRANSISTORS
Orbit sel
MAIN BC CLOCK
MAIN BC
TTC meeting, 2nd of May 2006
28
DESIGN [Technology choices]
Diff LVPECL
BC1
Sinusoidal frequencies
40.07XX MHz
varying
0.6V pk-pk /8
or 0.6V pk-pk (CMS)
CAPACITIVE
COUPLING +
THEVENIN
TERMINATION FOR
DC LEVEL OF 1.2V
Sine2
Square
Diff
NECL
Diff LVPECL
MUX2:1
Sine2
Square
Diff
NECL
Diff LVPECL
LVDS
800mV swing
Diff
NECL
ECL
V_comp3
comparator
AD96685
BC1 ECL/OUT
ECL Driver
BC1 NIM/OUT
PECL2NIM
PLL&
VCXO
LVDS
LVDS
FAN1:4
PECL
BC2 ECL/OUT
ECL Driver
BC2 lock
LVDS
800mV swing
Diff LVPECL
MUX2:1
AC
COUPLING
LVDS2ECL
text
Phase
Adjust
BC2 NIM/OUT
PECL2NIM
BCref_CLOCK
LVPECL2LVDS
PLL&
VCXO
LVDS
LVDS
FAN1:4
PECL
BCref
ECL/OUT
ECL Driver
BCref lock
BCref
NIM/OUT
LVDS2ECL
DELAY25
Orbit
detect
V_comp4
2.5V
CMOS
MAIN BC
NIM/OUT
PECL2NIM
ECL2NIM
CONVERSION
USING BSR17A
TRANSISTORS
MAIN BC
Fine
Delay
2.5V
CMOS
BC1 lock
BC2 lock
BCref lock
MAIN BC lock
RF2TTC BOARD
BLOCK DIAGRAM V1.7
28/04/2006
Fine
Delay
2.5V
CMOS
Orbit1
Orbit2
Lock, TTCready, ...
DACs
& Ref
Voltage
BC & ORBIT SOURCES
SELECTION, DACs
adjustment for Orbit
comparators
I2C interface
BOARD STATUS
D
SET
CLR
Q
Multiplexer
S1
D
Coarse
Delay
S4
C2
ENB
BC1 CLOCK
Multiplexer
S1
MACHINE MODES
INTERNAL
CNT
FINE DELAYS CONTROL
REMOTE
CONTROL
BST decoder
D
SET
CLR
ORBIT1
NIM/OUT
Adjust.
Stretch
er
ECL2NIM
BC2_clock
Q
C1
Q
C2
ORBIT2
NECL/OUT
ENB
BC2 CLOCK
ECL Driver
Fine
text
Delay
ECL2NIM
INTERNAL
CNT
SET
VME INTERFACE
STATUS REGISTERS
CLR
Q
SET
CLR
INTERNAL CLOCK
C1
Q
Q
MAIN ORBIT
NECL/OUT
D
Coarse
Delay
S4
Adjust.
Stretch
er
Q
Sync
ORBIT2
NIM/OUT
Multiplexer
S1
Sync
D
Sophie BARON, PH-ESS
LVDS2ECL
Coarse
Delay
ORBIT1
NECL/OUT
ECL Driver
LVDS2ECL
D
INTERNAL
CLOCK
Fine
Delay
D
S4
Sync
VME BUS
VME BACKPLANE
BC1_clock
VME access
VME_Berr
BST_ready
NECL
C1
Orbit sel
TTCrx
Adjust.
Stretch
er
MC10EP89 ECL
coax cable
drivers
Q
Sync
MACHINE MODES
LVCMOS
(2.5V)
Machine Mode Run/No
INTERNAL
CNT
V_comp5
LVCMOSLVTTL (3.3V)
MAIN BC int/BC1
BC2/Bcref
MAIN ORBIT Or1/Or2/
Int
74AHC123
BCsel[1..0]
LVDS (2.5V)
DELAY25
text
2.5V
CMOS
ECL
(NECL, PECL,
LVPECL)
FAN1:4
Orb2 det
40 ns LVPECL
Stretch
er
MAIN BC
ECL/OUT
ECL Driver
MAIN BC lock
DELAY25
5ns
square
pulse
ECL
comparator
AD96685
DELAY25
Step 500ps, range 25ns
LVDS
LVDS2ECL
Orb1 det
40 ns LVPECL
Stretch
er
PECL
PLL&
VCXO
LVDS
MAIN BC
sel[1..0]
I2C
Orbit
detect
QPLL
Phase
Adjust
LVPECL2LVDS
INTERNAL
CLOCK
5ns
square
pulse
Sine2
Square
LVDS
800mV swing
MUX4:1
Diff LVPECL
LVPECL QUARTZ
80.158MHz
Sine2
Square
PECL2NIM
FAN1:4
AC
COUPLING
BST
SIGNAL
OPTICAL
TTC
FRAMES
PECL
BC2_CLOCK
BCref sel
Diff LVPECL
PLL&
VCXO
FROM RF OPTICAL
RECEIVERS
Phase
Adjust
LVPECL2LVDS
Diff LVPECL
ORBIT2
FAN1:4
BC1 lock
BC2sel
Sine2
Square
BC ref
Sine pulse
1V peak (0-1V)
5ns width
LVDS
LVDS2ECL
MUX2:1
AC
COUPLING
V_comp2
ORBIT1
PLL&
VCXO
LVDS
Diff LVPECL
v
BC2
Sinusoidal frequency
40.07XX MHz
fixed
0.6V pk-pk / 8
or 0.6V pk-pk (CMS)
Phase
Adjust
LVPECL2LVDS
BC1sel
V_comp1
BC1_CLOCK
LVDS
800mV swing
Diff LVPECL
AC
COUPLING
MC10EP89 ECL
coax cable
drivers
QPLL
C2
Fine
Delay
ECL Driver
LVDS2ECL
ENB
ECL2NIM
Orbit sel
MAIN BC CLOCK
FPGA
MAIN BC


TTC meeting, 2nd of May 2006
MAIN ORBIT
NIM/OUT
ECL2NIM
CONVERSION
USING BSR17A
TRANSISTORS
ECL/LVDS components
LVDS 2 ECL conversion application note
29
DESIGN [Schematics & Features]
See schematics
 Coupling considerations
 Conversions
o
o
o
o
o
ECL2LVDS
LVDS2PECL
PECL2NIM
NECL2NIM
ECL2CMOS
 BC & Orbit inputs
o Coupling
o Comparator choice
o Voltage reference adjustment
 Internal clock
o Fixed oscillator
o ECL differential clock lines
 Orbit synchronisation process
o Pulse lengthening
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
30
DESIGN [Schematics & Features]
See schematics
 Use of CERN ASICS
o Delay25
o QPLL
 FPGA
o
o
o
o
o
Device choice
Programming modes
Signal levels
Pinout and I/o Banks
Firmware consideration
• VME interface => implemented in the ATLAS TRT-TTC board
• Triple logic necessary for critical registers? (working modes, auto_config)
 Internal communication busses
o I2C
 ECL output drivers
o MC100EL89 coax cable drivers
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
31
DESIGN [Schematics & Features]
See schematics
 Power considerations
o Estimation
o Solutions
 Debugging facilities
o Test points
o Spare connector
o Signal tap
 Bugs to be corrected
o Missing pull-up resistors
 PCB design
o Front Panel
o Layout
 Prototyping
o
o
o
o
Price estimation: components about 830 $
Quantities
Component procurement
Schedules
Sophie BARON, PH-ESS
TTC meeting, 2nd of May 2006
32




Sophie BARON, PH-ESS
Receiver Crate
Functionalities
Design
AOB
TTC meeting, 2nd of May 2006
33