Transcript REUSE - 전남대학교

Reuse Methodology
for System-On-Chip Designs
전남대학교 정보통신공학부
교수 김 영 철
[email protected]
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Agenda
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Mobile Society Change
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2.
II.
PC -> Mobile Communication
Component -> System
Design Methodology
1.
2.
ASIC Design Flow
SoC Design Flow
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Shift 1: From PC to Communications Centric
Services
Broadband
Network
100Mb/sWLAN
RF
20Gop/s
WWW
Java
Configurable
Multi-Standard
Info Plug...
<1 Watt
LAN
MPEG 4-7
100 Gop/s
??
5 Gtr/s
10 Watt
-> Domain Specific3Computing
Mobile Society의 환경 변화
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PC 시대의 시작
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Internet 시대의 시작
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1995년 전후로 한 Analog Mobile Phone, Digital Phone
시대의 시작
3세대 IMT-2000 시대의 시작을 앞두고 있음
Post PC 시대의 시작
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PC 통신, E-mail (WS, PC), WWW 시대의 시작
Mobile Phone 시대의 시작
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1980년을 전후로 하여 8-bit/64K Memory PC 시대의 시
작
다양한 형태의 PDA를 중심으로 한 Post PC
Network Information Appliance 시대를 위한 준비
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Post-PC Silicon System in 2006
80nm , 200M+ Transistors
www
gps
Speech
Pen
Vision
Bio
Motion
Security
Sensors
RF / Analog
20 MByte
32 Bit ASPP’s Distributed
Memory
Embedded
Software
200MHz
<1 Watt
<1 Volt
Re-configurable Interconnect
1 M gate
1 M Gate
Re-configurable
Hardwired
Computing
Logic
Display
Sound
Data
Bio
Actuators
50 GIPS-500GOPS
ENERGY/OP : 100
FLEXIBILITY - REUSE - IP
More than IP assembly!!
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Productivity Gap in Hardware Design
Source: sematech97
A growing gap between design complexity and design productivity
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100,000
Logic transistors per chip ( millions )
10,000
G
F
58% CAGR
E
C, D
21% CAGR
A, B
0.001
1981
1995
0.01
2009
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Productivity
(thousands of transistors per staff month)
Increasing Designer Productivity
ASIC Design - Technology Diffusion
Technology Diffusion is Accelerating
PCS
PCs
Cellular
VCRs
Color
TV
Cable
TV
Black &
White TV
1 Million
0.5
1
5
10
15
Years to 1 Million Sales
Mobile and Wireless Communications - Richard Siber (617) 982-9500
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ASIC Design - Profit Loss
40
33
22
30
20
10
4
0
+50% develp. Cost
+9% Product Cost
+6 month develp.Time
Source: McKinsey
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Contents
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Foreword & Preface
Introduction
System-on-a-Chip Design Process
System-Level Design Issues: Rules
and Tools
Macro Design Process
RTL Coding Guidelines
Macro Synthesis Guidelines
Macro Verification Guideline
Contents(2)
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Developing Hard Macros
Macro Deployment: Packaging for
Reuse
System Integration with Reusable
Macro
System-Level Verification Issues
Data and Project Management
Implementing Reuse-Based SoC
Designs
Foreword
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Era of multimillion-gate chips
100 M gates and 3 GHz by 2008 (Sematech)
100 gates/day -> 5000 years to complete
-> $500 million in today’s dollars
How will we get there?
Reusable IP(Intellectual Property) is essential
Better, Faster, Cheaper devices consumers expect
Foreword
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Synopsys and Mentor Graphics joins forces to help
make IP reuse a reality
-> Reuse Methodology Manual
Preface
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Every chapter with additional information
- Based on suggestions from readers and
on our own experiences
- Added some new materials on low-power design
for reuse
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Fundamental theme of any good design discipline:
Concept of Locality
- Use a fully synchronous design style
- Do rigorous, bottom up verification
- Plan before doing
Chapter 1. Introduction
Silicon technology to build chips consisting of tens
of millions of gates
- Current design tools and methodologies as
inadequate for developing million gate ASICs
- Pressure to keep design team size and design
schedules constant as design complexities grow
- Tools are not providing the productivity gains
- The use of predesigned and pre-verified cores:
Bridging the gap between available gate-count and
designer productivity
- Attempt to capture and incrementally improve on
current best practices in the industry, and to give a
coherent, integrated view of design process
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1.1 Goals of This document
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Common set of problems facing everyone
– Time-to-market pressure
- Quality of results, in performance, area, and power
- Increasing chip complexity -> verification more
difficult
- The development team has different levels and
areas of expertise
- Hard to reuse previous designs
- SoC designs include embedded processor core,
and thus significant software component
-> leads to additional methodology, process, and
organizational challenges.
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Effective design reuse strategies
– How reusable macros fit into an SoC
development methodology
- How to design reusable soft macros
- How to design reusable hard macros
- How to integrate soft and hard macros into
an SoC design
- How to verify timing and functionality in
large SoC design
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Deep submicron techinology presents a whole
set of design challenges:
– Interconnct delays
- Clock and power distribution
- place and route of millions of gates
- Interconnect issues, floorplanning, and
timing design must be addressed early in the
design process
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1.1.1 Assumptions & Definitions
Assumptions
- HDL design and synthesis
- Design for test, including full-scan techniques
- Floorplanning, physical synthesis, and place and
route
 Definitions
– Macro, Core, Block, IP -> Interchangable terms
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- Subblock: subcomponent of a macro
- Soft macro: deliverable one to integrator as
synthesizable RTL code
- Hard Macro: deliverable one to the integrator as a
GDSII file
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1.1.3 Virtual Socket Interface Alliance
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VSIA
- An Industry group working to facilitate the adoption
of design reuse by setting standards for tool
interfaces and design and documentation practices
- WGs of VSIA have developed a number of
proposals for standards
– Virtual Component: VSIA adopted the name VC to
specify reusable macro
- Firm Macor: VSIA defined an intermediate form
between hard and soft macro that can be deliverable
in RTL or netlist form with or without detailed
placement.
1.2 Design for Reuse: The Challenge
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Principles for design reuse methodology
– Creation of every stage of design with the
understanding that it will be modified and reused in
other projects by other design teams
- The use of tools and processes that the design
information in a consistent, easy-to-communicate
form
- The use of tools and processes that make it easy to
integrate modules into a design when the original
designer is not available
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1.2.1 Design for Use
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To be reusable, a design must first be usable:
a robust and correct design
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Good design techniques
– Good documentation
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Good code
Thorough commenting
Well-designed verification environments and suites
Robust scripts
1.2.2 Design for Reuse
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The macro must be:
– Designed to solve a general problem
- Designed for use in multiple technologies
- Designed for simulation with a variety of simulators
- Verified independently of the chip in which it will be
used
- Verified to a high level of confidence
- Fully documented in terms of appropriate
applications and restrictions
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1.2.3 Fundamental Problems
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The results of experience with problems such as:
– The design representation is not appropriate
- The design comes with incomplete design
informations
- Supporting scripts are not available
- The full design was never properly archieved
- The tools used to develop the design are no longer
supported
- The tools used to develop the design had poor
inter-operability
- A hard macro is available, but the simulation model
is so slow
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1.3 Emerging Business Model for Reuse
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Reuse is not just a technical issue:
– Most of the barriers to the adoption of reuse
are management and cultural in nature
- Look at the business and organization
context within which design and design
reuse occur
- The business models are important for
defining the cost-benefit equation that drives
when and how reuse occurs in real
organization
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1.3.1 Changing Roles in SoC Design
Role in traditional design
- Systems groups designed to the RTL level
- ASIC group did physical implementation for internal
and external customers
- Full custom chip design groups designed chips from
start to finish
 Role in SoC Design
- Systems house to focus on software and applications
aspects of the design
- ASIC vendor must do more of the chip integration,
manage the IP, and provide simulation and synthesis
models to the systems designers
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1.3.2 Retooling Skills for New Roles
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Significant retooling of design skills in the industry
– System houses are focused on improving software
and system architecture skills to differentiate their
products
- Silicon providers to provide not just silicon, but IP
and integration services required to implement very
complex chips
- Design teams within these silicon providing
companies are developing skills and methodologies
for integrating IP into large designs
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1.3.3 Sources of IP for SoC Designs
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Cell phone chip with advanced features
– Design requires a 32-bit processor, a DSP, large
amounts of on-chip memory, numerous blocks from
previous cell-phone designs, and some new
designs for the Internet support blocks
- Silicon vendor may provide the processor and DSP
- The memory designed by using a memory generator
from the silicon vendor
- The rest of the blocks from internal sources:
Reusing blocks from previous design and
developing new blocks
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1.3.3 Sources of IP for SoC Designs
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Semiconductor company making automotive chips
– Design requires on-chip, 32-bit processor and large
amounts of memory plus many blocks from previous
generations of designs
- The new design integrates multiple chips into one
new chip
- The processor may be a proprietary processor from
another group in the company
- Half or more of the other blocks are from other
internal groups, who designed the different chips
that made up the previous generation chip set
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1.3.4 Cost Models Drives Reuse
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Business justification for investing in making designs
reusable
– Integrating a highly reusable block requires on tenth
or less the effort of developing that same block for a
single use: 10 times productivity benefit or higher for
that part of the design
- For not fully designed for reuse,
5 times productivity benefit in using a block that has
been designed for reuse, over reusing a block that
was not designed for reuse
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1.3.5 How Much Reuse and When
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Which blocks should be designed for reuse
– 10 times productivity benefit over ten or more chip
designs justifies the reuse efforts:
Processor, their peripherals, standard interfaces
such as PCI and USB
- For domain specific blocks such as multi-media or
data communication blocks deserve full design-forreuse if used on several generations of product
- Application specific blocks may well not justify the
effort to make them reusable
- For blocks that will only be used three or four times,
such blocks do not warrant full design for reuse, but
justify some effort toward reusability