Transcript 951023_03

AN ENCODER FOR A 5GS/S 4-BIT
FLASH ADC IN 0.18μM CMOS
Samad Sheikhaei, Shahriar Mirabbasi, and
Andre Ivanov , IEEE International Symposium
on Circuits and Systems, May 2005
班級 ：積體碩一
姓名 ：黃順和
學號 ：95662009
outline
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1. Introduction
2. Design of the Encoder
3. Gray Code
4. Bubble errors
5. CML Implementation
6. Simulation Results
7. Conclusions
8. References
Introduction
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In the encoder presented in this paper, a two-stage pipelined
architecture is utilized to enhance the speed of the circuit.
An encoder circuitry translates this thermometer code to an
intermediate Gray code , then converts the Gray code to a
binary code.
To further increase the speed and to handle the low swing
output signals of the comparators, the encoder is implemented
using CML blocks.
Design of the Encoder
Schematic of a simple encoder
No pipelining
2-stage pipelining
Gray Code
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將 1 1 0 1 0 1 (Gray)轉換成二進碼
Bubble errors
CML Implementation
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Have a NAND/AND gate, an XOR gate and a
latch in CML circuits.
All the signals in the circuit are differential and low
swing.
As all the clocked transistors in the circuit are
differential pairs.
Simulation Results
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A bias current of 100μA is used for all the
gates and the latches in a 0.18μm CMOS
technology with a 1.8V supply.
As shown in this table, a 2-stage pipelining
improves the operation speed of the encoder
from 3.5GHz to 5GHz.
Conclusions
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Gray coding is used as an intermediate step
to minimize the effect of bubble errors.
To increase the speed of the encoder, CML
circuits are used.
Simulations show that a 2-stage pipelining is
required to achieve the 5GHz operating
frequency.
References
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[1] L.Y. Nathawad, R. Urata, B.A. Wooley and D.A.B. Miller,“A 40-GHz Bandwidth, 4-bit,
Time-Interleaved A/D Converter Using Photoconductive Sampling,” IEEE Journal of SolidState Circuits, vol. 38, no. 12, pp. 2021 - 2030, Dec. 2003.
[2] K. Lee, W. Namgoong, “A 0.25μm CMOS 3b 12.5GS/s Frequency Channelized
Receiver for Serial-Links,” ISSCC Dig. Tech. Papers, pp. 336-337, Feb. 2005.
[3] W. Ellersick, K. Yang, M. Horowitz, and W. Dally, “GAD: A 12GS/s CMOS 4-bit A/D
Converter for an Equalized Multilevel Link,” IEEE Symposium on VLSI Circuits, pp. 49–
52, June 1999.
[4] S. Sheikhaei, S. Mirabbasi, A. Ivanov, “A 4-bit 5GS/s flash A/D converter in 0.18μm
CMOS,” to be presented at the IEEE International Symposium on Circuits and Systems,
May2005.
[5] B. Razavi, Principles of Data Conversion System Design,IEEE Press, 1995.
[6] C. S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U.Voegeli, and Z. Wang, “A
family of low-power truly modular programmable dividers in standard 0.35μm CMOS
technology,” IEEE Journal of Solid-State Circuits, vol. 35, no.7, pp. 1039–1045, July
2000.