Transcript project_overview & plan

Giga-Scale System-On-A-Chip
International Center on System-on-a-Chip (ICSOC)
Jason Cong
University of California, Los Angeles
Tel: 310-206-2775, Email: [email protected]
(Other participants are listed inside)
Background: “Double Exponential” Growth of
Design Complexity
• C1: complexity due to exponential increase of chip capacity
– More devices
– More power
– Heterogeneous integration, ……
• C2: complexity due to exponential decrease of feature size
– Interconnect delay
– Coupling noise
– EMI, ……
• Design Complexity  C1 x C2
Jason Cong
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10,000,000
100,000,000
1,000,000
100,000
10,000
10,000,000
58%/Yr. Complexity
growth rate
1,000,000
100,000
1,000
10,000
xx
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21%/Yr.
Productivity growth rate
x
100
xx
x
x
x
1,000
100
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Transistor/Staff-Month
Logic Transistors/Chip (K)
Motivation: Productivity Gap
10
1998
2003
Chip Capacity and Designer Productivity
Jason Cong
Source: NTRS’97
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Project Summary
• Develop new design methodology to enable efficient
giga-scale integration for system-on-a-chip (SOC)
designs
• Project includes three major components
– SOC synthesis tools and methodologies
– SOC verification, test, and diagnosis
– SOC design driver – network processor
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Current Research Team
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US
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Taiwan
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NTHU: Shi-Yu Huang, Tingting Hwang, J. K. Lee,
Youn-Long Lin, C. L. Liu, Cheng-Wen Wu, Allen Wu
NCTU: Jing-Yang Jou
China
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UCLA: Jason Cong
UC Santa Barbara: Tim Cheng
Tsinghua Univ.: Jinian Bian, Xianlong Hong, Zeyi Wang,
Hongxi Xue
Peking Univ.: Xu Cheng
Zhejiang Univ.: Xiaolang Yan
Several new faculty members in the 7 institutions
Guest members from National University of Singapore, Purdue
Univ., UCLA (EE Dept), and UT Austin
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Thrust 1 -- SOC Synthesis Environment/Methodology
(Led by Jason Cong)
Design Spec
VHDL/C
VHDL/C
Co-Simulation
Design Partitioning
ASIC Synthesis
Code Generation for
Retargetable Compiler
and Assembler
Generator
DSP Synthesis
and
Optimization
FPGA Synthesis
and Technology
Mapping
Interconnect-Driven
High-level Synthesis
Synthesis for
IP Reuse
Physical Synthesis for
Full-Chip Assembly
Embedded
Processors
Jason Cong
DSPs
Embedded
FPGAs
Customiz
ed Logic
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Highlights of Accomplishments
• Novel microarchitecture and system methodology for multi-cycle
on-chip communication
– ISPD’03, ICCAD’03, DAC’04, T-CAD
• Optimality study of large-scale circuit placement
– ASPDAC’03, ISPD’03, ICCAD’03, T-CAD
• Floorplanning with interconnect planning
– About 30 papers published in DAC, ICCAD, ISPD, ASPDAC, ISCAS
and Transactions
• P/G Network Analysis & Optimization
– ICCAD’01, T-CAD, ASPDAC’04
• Parasitic R/L/C extraction
– ASPDAC, ASICON and IEEE Transaction on MTT
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Thrust 2 -- SOC Verification, Test, and Diagnosis
(Led by Tim Cheng)
Verification and
Testing
Testing and diagnosis
for heterogeneous SOC
Self-testing using
on-chip
programmable
components
Self-testing for onchip analog/mixedsignal components
New test techniques
for deep-submicron
embedded memories
Jason Cong
Enabling techniques for semiformal functional verification
Scalable constraintsolving techniques
Automatic/semiautomatic functional
vector generation
from HDL code
Integrated framework for
simulation, vector generation
and model checking
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Highlight of Accomplishments
• Developed and released ATPG-based SAT solvers for
circuits
– DATE2003, DAC2003, ICCAD2003, HLDVT2003 and ASPDAC2004
• A new Statistical Delay Testing and Diagnosis
framework consisting of five major components
– DAC’02, ICCAD’02, DATE’03, DAC’03
• On-Chip Jitter Extraction for Bit-Error-Rate (BER) Testing of
Multi-GHz Signal
– ASPDAC2004 and DATE2004
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Thrust 3 – Design Driver: Network Security Processor
(Led by Prof. C. W. Wu & Xu Cheng)
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Applications: IPSec, SSL, VPN, etc.
Functionalities:
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Public key: RSA, ECC
Secret key: AES
Hashing (Message authentication): HMAC (SHA-1/MD5)
Truly random number generator (FIPS 140-1,140-2 compliant)
Target technology: 0.18m or below
Clock rate: 200MHz or higher (internal)
32-bit data and instruction word
10Gbps (OC192)
Power: 1 to 10mW/MHz at 3V (LP to HP)
Die size: 50mm2
On-chip bus: AMBA (Advanced Microcontroller Bus Architecture)
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Highlights of Accomplishments
• Security processor – encryption module
– Secret key encryption module
• Operations:
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– Matrix operations, manipulation
AES cryptography
32-bit external interface
58K gates
Over 200MHz clock
Throughput: 2Gbps
Support key length of 128/192/256 bits
• Microprocessor -- Unity Processor
– Used in over 7,000 NetPCs
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International Collaborations
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Joint NSF/NSC workshop in Aug. 1999 on SOC (Hsin-Chu, Taiwan)
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1st team preparation meeting for the proposed center in Jan. 2000 (Yokohama, Japan)
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2nd planning meeting held in April 2000 (Hawaii, US)
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3rd planning meeting in Aug. 2000 (Chengde, China)
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Proposal submitted to NSF in Aug. 2000 and funded in Dec. 2000
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Workshops
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March 30-31, 2001 in Taipei, Taiwan.
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June 23-24, 2001 in Los Angeles, USA
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August 31-September 1, 2001 in HangZhou, China
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March 28-29, 2002, National Tsing Hua University, Hsinchu, Taiwan
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August 20-21, 2002, Peking University, Beijing, China
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November 15-16, 2002, University of California, Santa Barbara
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March 27-29, 2003, National Taiwan University, Taipei, Taiwan
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December 19-21, 2003, Yunnan University, Kunming, China
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Publications
• 220 research publications up to this point
• 67 in top conferences/journals in the field (DAC,
ICCAD, DATE, ASPDAC, ITC, FPGA, ISLEPD, TCAD, TODAES, etc.)
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People & Education
• Many interactions among participants from different
institutes
• Two new IEEE fellows:
– Prof. Xiaolang Hong, Tsinghua Univ.
– Prof. Cheng-Wen Wu, National Tsing Hua Univ.
• Involved many young faculty members and researchers
• Trained an army of graduate students
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Complexity Management for Future Micro
and Nano Systems
• Higher level of abstraction (without losing physical
reality)
• Reliability and reconfigurability
• Fundamental algorithms for future design automation
tools of micro and nano systems
• Education
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Participants
• US
– UCLA and UCSB
• Taiwan
– National Tsing Hua Univ.
– National Taiwan Univ. ??
• China
– Tsinghua Univ.
– ??
• Japan ??
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