Transcript 100 krad(SiO 2 ) - Vanderbilt University

Effects of Device Aging on Microelectronics
Radiation Response and Reliability
D. M. Fleetwood, M. P. Rodgers, L. Tsetseris, X. J. Zhou,
I. Batyrev, S. Wang, R. D. Schrimpf, and S. T. Pantelides
Vanderbilt University, Nashville, TN 37235
([email protected])
Work supported in part by AFOSR MURI and US Navy
Outline
• Previous Work
– Effects of burn-in, pre-irradiation temperature stress
– Aging and baking effects on unpassivated capacitors
• Aging effects on transistors
– Parts stored in a non-hermetic environment
– Parts stored hermetically sealed
– Humidity testing
• Density functional theory calculations
• Hardness assurance implications
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Effects of pre-irradiation elevated temperature stress
Example of burn-in reducing
interface traps in gate oxide
M. R. Shaneyfelt, et al., IEEE Trans. Nucl. Sci.
vol. 41, 2550 (1994)
Example of pre-rad temperature
stress reducing oxide traps
in field oxide
M. R. Shaneyfelt, et al., IEEE Trans. Nucl. Sci.,
vol. 43, 865, 1996.
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Aging effects in unpassivated, Al gate capacitors
tox = 33 nm; bias during rad = 5 V; bias during bake = 0 V
0.6
Unbaked
baked
1986
0.8
DNit (1012 cm-2)
DN
DNotot(10
(101212cm
cm-2-2))
1
0.6
0.4
0.2
0
Unbaked
baked
0.4
0.2
0
0
200
400
600
800 1000 1200
Dose [krad(SiO2)]
0
200
400
600
800 1000 1200
Dose [krad(SiO2)]
A. P. Karmarkar, B. K. Choi, R. D. Schrimpf, and D. M. Fleetwood,
IEEE Trans. Nucl. Sci., vol. 48, pp. 2158-2163, 2001.
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Experimental Details: Aging Study
•
Fully processed and
passivated poly-Si gate MOS
transistors
–
–
–
•
•
•
•
32 nm, stored non-hermetically
60 nm, stored hermetically
60 nm, stored non-hermetically
Parts from same lot well
characterized in 1988
10-keV X-ray irradiation at
dose rates of 100 and 850
rad(SiO2)/s for 60 and 32 nm,
parts respectively
6 V bias applied to all nMOS
gates with all other pins held
at ground, for rad + anneal
Midgap method of Winokur
and McWhorter used to
estimate ∆Vot and ∆Vit
WINOKUR etal. 1987
D. M. Fleetwood et al. IEEE TNS Vol. 35,
No. 6, 1497, Dec. 1988
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Test Procedure: 32 nm, non-hermetically stored
1988
Parts were packaged
& hermetically sealed
in 1987
Parts were irradiated to
500 krad(SiO2)
Parts were
delidded
Parts were stored
Parts were stored
(not hermetically
sealed)
2005
3 of the 6 parts were
baked @ 200C with
all pins grounded
prior to irradiation
(PETS)
Half of the parts
were not baked
Data recorded throughout
the postirradiation anneal.
(room temperature)
Parts were irradiated to
500 krad(SiO2)
Data recorded throughout
the postirradiation anneal.
(room temperature)
2 months after irradiation
parts subjected to a high
temperature anneal parts
@ 100C
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32 nm devices, non-hermetic: ∆Vth
500 krad(SiO2)
M. P. Rodgers, D. M. Fleetwood, R. D. Schrimpf, I. G. Batyrev, S. Wang, and S. T. Pantelides,
IEEE Trans. Nucl. Sci. 52, 2642-2648 (2005).
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32 nm devices, non-hermetic: ∆Vit
500 krad(SiO2)
M. P. Rodgers, D. M. Fleetwood, R. D. Schrimpf, I. G. Batyrev, S. Wang, and S. T. Pantelides,
IEEE Trans. Nucl. Sci. 52, 2642-2648 (2005).
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32 nm devices, non-hermetic: ∆Vot
500 krad(SiO2)
M. P. Rodgers, D. M. Fleetwood, R. D. Schrimpf, I. G. Batyrev, S. Wang, and S. T. Pantelides,
IEEE Trans. Nucl. Sci. 52, 2642-2648 (2005).
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Test Procedure: 60 nm, hermetically stored
Parts were packaged
& hermetically sealed
in 1987
1988
Parts were stored
2005
Parts were delidded &
irradiated to
100 krad(SiO2)
Data recorded throughout
the postirradiation anneal.
(room temperature)
Half of the parts were
baked @ 200C with all
pins grounded prior to
irradiation (PETS)
Parts were
delidded
Half of the parts were
not baked
Parts were irradiated to
100 krad(SiO2)
Data recorded throughout
the postirradiation anneal.
(room temperature)
2 months after irradiation
parts subjected to a high
temperature anneal parts
@ 100C
10
60 nm devices, hermetic: ∆Vth
100 krad(SiO2)
M. P. Rodgers, D. M. Fleetwood, R. D. Schrimpf, I. G. Batyrev, S. Wang, and S. T. Pantelides,
IEEE Trans. Nucl. Sci. 52, 2642-2648 (2005).
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32 nm devices, non-hermetic: ∆Vit
100 krad(SiO2)
M. P. Rodgers, D. M. Fleetwood, R. D. Schrimpf, I. G. Batyrev, S. Wang, and S. T. Pantelides,
IEEE Trans. Nucl. Sci. 52, 2642-2648 (2005).
12
32 nm devices, non-hermetic: ∆Vot
100 krad(SiO2)
M. P. Rodgers, D. M. Fleetwood, R. D. Schrimpf, I. G. Batyrev, S. Wang, and S. T. Pantelides,
IEEE Trans. Nucl. Sci. 52, 2642-2648 (2005).
13
60 nm devices: stored non-hermetically
Dose: 100 krad(SiO2); 6V bias
Similar enhancement in interface-trap buildup to 32 nm
devices, stored non-hermetically
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Source of extra hydrogen
Left: Water complex consisting of two SiOH (silanol) groups and
a broken ring [energy = +(0.3-0.7) eV]
Right: Water complex consisting of two SiOH groups and no
broken ring [energy = -0.3 eV].
Water that diffuses into SiO2 naturally dissociates, providing
extra H+ to enhance interface-trap formation
M. P. Rodgers, et al., IEEE Trans. Nucl. Sci. 52, 2642-2648 (2005).
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Supporting evidence: humidity testing
130C at 85% Relative Humidity; 0 V
Rad: 100k, 6V
Anneal, 6V
Enhancement due to increased interface-trap
buildup during post-irradiation anneal
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Implications for hardness assurance
•
•
•
•
Irradiate to spec level
50 - 300 rad(Si)/s
50% margin in irradiation not
sufficient to describe aginginduced increase in for nonhermetically stored devices
Exposing parts to PETS does
not simulate the aging effects
observed in these parts
Additional margins required in
hardness assurance testing for
parts susceptible to enhanced
interface-trap buildup during
aging
Combining the aging and PETS
effects shown may explain
previous complications in lowdose-rate response of MOS and
bipolar devices
Electrical Test
< 2 hr

Biased Anneal
@ T=25 C
Pass ?
No
Electrical Test
Yes
Irradiate to 0.5x spec
50 - 300 rad(Si)/s
Yes
Pass ?
Biased Anneal
168 hr @ 100 C

No
Reject
Parts
Electrical Test
< 2 hr
Parts
OK
Yes
Pass ?
No
Reject
Parts
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Conclusions
• Radiation response of MOS devices can change significantly
with aging time after processing and/or packaging.
– Effects are most significant for interface trap buildup during postirradiation annealing.
• Theory, as supported by the results of humidity tests, suggests
that the increase in degradation is associated with H2O or other
H-containing complexes.
• Non-hermetic environments are especially challenging.
– How hermetic is hermetic enough?
– Some effects seen even for hermetic environments, likely due to
on-chip sources of hydrogen.
• Extra margins required in lot acceptance testing for sensitive
devices/environments.
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