Transcript Trigger System

Status of the electronics systems
of the MEG experiment
PSI - Jul. 19th, 2005
1
Electronic chain
HV
front PMT
216
Active
Splitter
1:1
1:1
4:1
lateral PMT
612
Active
Splitter
1:1
1:1
4:1
Active
Splitter
1:1
1:1
4:1
LXe
HV
60
bars PMT
TC
Ramp
Pre-Amp
DRS
DRS
DRS
DRS
DRS
DRS
8:1
640
HV
Wires
Pre-Amp
Strips
Pre-Amp
PSI - Jul. 19th, 2005
Trigger
Trigger
Trigger
3 crates
HV
fibers APD
DC
120
atten
6 crates
32
576
1156
Aux. devices
Hit
registers
4 boards
2
DAQ and control
pE5 area
‘counting room’
Trigger
clock
start
stop
sync
Ancillary
system
Trigger
Trigger
Trigger
3 crates
Busy
Error
Run start
Run stop
Trigger config
DRS
DRS
DRS
DRS
DRS
DRS
20 MHz
clock
Hit
registers
6 crates
PSI - Jul. 19th, 2005
Front-End PCs
Main DAQ PC
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
Gigabit
Ethernet
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
Trigger signal
Event number
Trigger type
storage
Event
builder
On-line farm
3
HV
PSI - Jul. 19th, 2005
4
HV System
4 different requirements:
–
–
–
–
Lxe: 1000V , 100 uA
TC bars: 2400V, 1 mA
TC curved: 500V, <1 uA
DC: 2400V, ~1 uA
• System works from 10V – 2400V, 1.5mA, 1uA resolution,
special version for 1nA resolution
• Current-trip feature implemented and tested, the HV-off
time determined by de-charging capacitance
http://www.fischerconnectors.com/
• HV will “end” at backplane
• ‘Users’ have to decide about connectors
1-15 kV
• 4-channel system in 3HE crate
(40 channels are currently in use at PSI)
• 10-channel system in 6HE crate
400 channels in preparation, ready by September
PSI - Jul. 19th, 2005
5
HV crate
• 10 chn per board
• 180 chn per 3 HE crate
• Back side connector
PSI - Jul. 19th, 2005
HV passes through backplane
6
Splitters
PSI - Jul. 19th, 2005
7
Splitter – project requirements
•
Inputs:
•
Test:
•
Outputs:
–
–
–
828 Lxe + 120 TC channels
Single ended (Rin=50Ω)
Dual row headers connectors
–
High-precision and constant amplitude levels
–
DRS:
–
Trigger:
–
Analog Adder:
–
–
Differential (Rout=120Ω)
Standard profile boxed header connectors (3M
–
Limited into 0V - 2.5V
–
–
Standard double Eurocard (6U)
16 channels per card
•
•
Full bandwidth
Gain ~ 1
•
•
100 MHz bandwidth
Gain ~ 1
•
•
•
4-channels sum
100 MHz bandwidth
Gain ~ 1
•
Dynamic range:
•
Card size and density:
PSI - Jul. 19th, 2005
input
DRS output
test
Trigger or
Spare output
DRS or trigger
summed output
8
Components selected
•
THS4509 – 1.9GHz, 6600 V/μs Low Distortion fully Differential
Amplifier
– DRS outputs driver;
•
AD8137 – Low Distortion Differential ADC Driver
– Trigger and sum output driver.
PSI - Jul. 19th, 2005
9
Prototype
•
In the first half of 2005 the
technical requirements for
splitter were defined
•
The final prototype design
started immediately
•
The 2-channels prototype was
completed in March 2005 and
tested
PSI - Jul. 19th, 2005
10
Crosstalk test
•
Input pulse:
–
–
1.6V amplitude (Vout+=+0.8V, Vout-=-0.8V)
<1 ns risetime
•
Input crosstalk (Metallic enclosure)
•
Inside the board + output connector
crosstalks (input connector contribution
excluded)
–
–
–
–
•
Crosstalk Ch1→Ch4: <0.1%;
Crosstalk Ch2→Ch4: ~0.5%;
Crosstalk Ch3→Ch4: ~1.5%;
Crosstalk Ch3→Ch4: ~1.5%
Inside the board crosstalk
–
Crosstalk Ch3→Ch4: ~0.5%;
PSI - Jul. 19th, 2005
11
Final splitter board
Full BW
Output
(34-pins)
Input
(64-pins)
Sum output
(16-pins)
Reduced BW
Output
(34-pins)
PSI - Jul. 19th, 2005
Power
and test
12
Test circuit
• The calibration of the DRS
channels needs constant levels
voltage on all inputs
• A step voltage generator, with 4
voltage levels, was developed
• Levels are defined with high
precision low noise reference IC
(LM4140) with
0.1% accuracy and
low temperature coefficient
(3ppm/°C)
• This circuit will be implemented on
the backplane and it will feed all the
splitter cards contained in the crate.
PSI - Jul. 19th, 2005
13
Production
•
•
•
•
October 05 – test of the final prototype
December 05 – end of full production
October 05 – order of the cables
March 05 – installation
PSI - Jul. 19th, 2005
14
TC
PSI - Jul. 19th, 2005
15
PMT ramp generator
B
to Splitter
Analog signals
to DRS and trigger
PMT
S
B
TC Analog Sign. Monitor
Passive
Splitter
6U Eurocards
boards
8 boards
PSI - Jul. 19th, 2005
D/D
RAMP
GEN.
to Splitters
Signals to DRS
Dual Threshold
Discriminator
NIM Signal
16
for any possible use
C1 10n
T1 2N3955
R3 10
IG1
145000 e-
-
T2 2N3955
R4 10
1ns
2 x MMBF4392
2 x OPA847
+ +
R8 330
V2 5
C3 100p R5 330
R1 100k
C2 80pR2 100k
V3 400
•
•
Input: 10 APD
Ouput:
–
R7 13k
-
VF3
+ +
–
DIS
DIS
U2 OPA847
U1 OPA847
•
•
•
V1 5
R6 100k
10 shaped and
discriminated channels
for the hit register
1 analog sum for the
trigger
ENC: 1500 e rms
Risetime:5 ns
Pulse-length: 50 ns
APD
Kapton Flex.
C4 1p
Black
Coating
----DIS
V4 5
Scint. Fibers
APD pre-amplifier
Electronics
boards -10
channels
Transition
board
Copper Cold
Finger(~20°)
Peltier
Cell
PSI - Jul. 19th, 2005
Heat
Exchanger
17
Hit encoder/register
6U VME boards
5 boards
Curved TC
left side
152
Mask
Left
Clock
control signal
Trigger
and
monitor
PSI - Jul. 19th, 2005
A*B
152
152
Curved TC
right side
Mask
Right
Encoder
Control
Logic
Register
VME bus
FPGA
18
Production
PMT ramp generator
• October 05 – design of the final board
• January 06 – system delivery (8 boards - 6U Eurocards)
APD pre amplifiers
• September 05 – design of the final APD pre-amplifiers
• October 05 – test of the final prototype
• December 05 – system delivery (80 cards)
APD hit registers
• December 05 – board design
• April 06 – system delivery (6 boards – 6U VME)
PSI - Jul. 19th, 2005
19
DC
PSI - Jul. 19th, 2005
20
DC electronics
At interface He bag –
outside Cobra
right
inverting
anode
OR
small R
left
Preamplifier
16 x (2 x 9) x 6 = 1728 channels
16 ch.
up +
cable
to DRS
up cathode
down +
OR
Large R
down Non inverting
PSI - Jul. 19th, 2005
21
Production
DC electronics
• September 05 – design of the final pre-amplifiers
• November 05 – test of the final prototype
• January 06 – system delivery
PSI - Jul. 19th, 2005
22
Trigger
PSI - Jul. 19th, 2005
23
Trigger system structure
2 boards
2 VME 6U
14 boards
LXe inner face
(216 PMTs)
16
Type1
Type1
Type1
1 VME 9U
14 x 48
Type2
4
2 x 48
Located on the platform
Type2
9+2 boards
LXe lateral faces
back (216 PMTs) 4 in 1 16
lat. (144x2 PMTs) 4 in 1 4
up/down (54x2 PMTs) 4 in 1
Type1
Type1
Type1
1 board
9 x 48
2 x 48
Type2
Type2
9 boards
Timing counters
curved (640 APDs) 8 in 1
u/d stream (30x2 PMTs)
16
Type1
Type1
Type1
2 x 48
1 board
9 x 48
4
Type2
1 board
Drift chambers
16+16 channels
PSI - Jul. 19th, 2005
2 boards
16
16
4
Type1
Type1
2 x 48
24
Type1 Present Status
CPLD :
• Type1 :
Coolrunner II (XC2C284-10-FG324) 
CPLD design completed and simulated 
FPGA :
• Type1-1:
• Type1-2
• Type1-3
• Type1-4
VIRTEX II- PRO (XC2VP20-7-FF1152) 
LXe front face (Frequency 116 MHz) 
LXe lateral faces in progress ~
TC x
DC x
PCB :
•
•
•
•
•
•
import FPGA 
Board Schematics 
Footprints and routing 
Gerber files 
PCB production in progress 
Board mounting x
PSI - Jul. 19th, 2005
25
Type1
PSI - Jul. 19th, 2005
26
Type2 Present Status
CPLD : Coolrunner II (XC2C284-10-FG324) 
• Type1 :
CPLD design completed and simulated 
FPGA : VIRTEX II- PRO (XC2VP40-7-FF1152) 
• Type2-0
Final Level completed 
• Type2-1
LXe inner faces x
• Type2-2
LXe lateral faces x
• Type2-3
TC x
PCB :
•
•
•
•
•
•
import FPGA 
Board Schematics 
Footprints and routing 
Gerber files 
PCB production in progress 
Board mounting x
PSI - Jul. 19th, 2005
27
Type2
PSI - Jul. 19th, 2005
28
Ancillary boards
Event counter
Trigger pattern
Type1
Type1
Type1
Busy
Type2
START
STOP
SYNC
RES
CLK
Type1
Type1
Type1
START
STOP
2
5
5
ANCILLARY Mother
CLK
20 MHz
...
5
PSI - Jul. 19th, 2005
from DAQ
Type2
Type2
5
ANCILLARY
Daughters
to DRS
SYNC
RES
5
2
5
60 x CLK
to DRS
VME
29
Ancillary Present Status
CPLD : Coolrunner II (XC2C284-10-FG324) 
• Type1 :
CPLD design completed and simulated 
Components :
PCB :
•
•
•
•
•
•
MAX9153 – 3D3418 
import FPGA 
Board Schematics 
Footprints and routing in progress 
Gerber files x
PCB production x
Board mounting x
PSI - Jul. 19th, 2005
30
Trigger components
All components already delivered,
including LVDS interconnect cables
PSI - Jul. 19th, 2005
31
Trigger test
• The test of the final boards can be done in September, as
foreseen in the schedule
• The test will be done by using Struck interfaces. The present
read-out speed of all trigger WFS for the full system is around
15 Hz.
• This rate is more than adequate for the trigger system needs:
calibration, efficiency measurements and stability
• We are investigating the possibility of increasing the readout
speed.
PSI - Jul. 19th, 2005
32
Trigger schedule
2002
2003
2004
2005
Prototype Board
Final Prototype
Full System
partial
installation
Prototype Board
Final Prototype
Full system
1st lot of
components
ordered
PSI - Jul. 19th, 2005
Design
Manufactoring
2nd lot of
components
full
install.
33
Assembly
Test
Milestone
Domino chip status
PSI - Jul. 19th, 2005
34
DRS2 plastic PLCC
•
PSI - Jul. 19th, 2005
674 additional chips produced
– 150 chips for MAGIC
– 4200 channels for DC/TC/LXe
35
Improved Sampling Range
Domino wave can be operated
below 500 MHz if started
with a longer starting pulse.
Minimum is ~5 MHz.
Modified start pulse makes
operation at 500 MHz stable.
PSI - Jul. 19th, 2005
36
Spikes in last beam time
PSI - Jul. 19th, 2005
37
Cause of spikes
At 33 MHz, spike is always sampled,
independent of FADC phase
At 16.5 MHz, FADC phase can be
adjusted to skip spike
PSI - Jul. 19th, 2005
38
Fixing spikes
before
Spikes were fixed by
reducing readout speed
from 33 MHz to 16.5 MHz.
Longer dead time will be
compensated by having
two FADCs in new
mezzanine board
after
PSI - Jul. 19th, 2005
39
Double Peaks
Double peaks in signals were
caused by crosstalk from domino
tap signal used for domino
frequency measurement
crosstalk
Domino Tap signal
Fix: different routing, multilayer,
ground shield
Clock signal
PSI - Jul. 19th, 2005
40
CMC connection
PSI - Jul. 19th, 2005
41
Timing Stability
Frequency Stabilization
Trigger Signal Sampling
8 inputs
domino wave
Freq.
Cntr
FPGA
16-bit
DAC
Implemented in FPGA (VHDL)
→ 400 ps stability
PSI - Jul. 19th, 2005
FAD
C
Low-jitter
clock
shift register
MUX
42
Recovery of Timing
4) Timing of all PMT pulses
is expressed relative to
t=0 point
f
2) Each DAQ card determines
and fits “Time-Zero-Edge” in
clock signal and uses this as
t=0
Domino speed stability of 10-3 :
PSI - Jul. 19th, 2005
50 ns
1) Trigger publishes phase
f of trigger signal f
relative to clock in
multiples of 10 ns
3) Measure pulse width of clock
to derive domino speed
400ps uncertainty for full window
25ps uncertainty for timing relative to edge
43
Domino wave jitter
30 ns
PSI - Jul. 19th, 2005
• 33 MHz calibration clock
• Peak fit with reference pulse
• Average over all pulses for
many events
• Jitter is 115 ps
• Maximum distance of any signal
to next clock peak is 15 ns →
accuracy should be ~60 ps
44
Calibration
• Measure Vin – Vout
characteristics with precise
DC power supply at the DRS2
input for all bins
• Fit characteristics and use it
for calibration
• One curve needed per bin,
under improvement
• Is now done offline, will later
be done online (front-end or
FPGA)
mV
ADC counts / 10
PSI - Jul. 19th, 2005
45
Effect of calibration
• Calibration in mV
• “Fixed pattern noise” is gone
• Crosstalk from clock remains
PSI - Jul. 19th, 2005
46
Noise Measurement
Trigger
mV
0.55 mV / 1V
> 11 bits
PSI - Jul. 19th, 2005
mV
47
Crosstalk inside DRS
Rise time
0→1
0→2
0→7
2 ns
2.8 %
1.6%
1.3%
8 ns
1.1 %
0.6%
0.8%
• Measured with signal generator
• Current crosstalk is not good but acceptable for the moment
• Since integral of crosstalk is zero, it should mainly affect the timing
and pile-up recognition
• Expect crosstalk in DRS3 (differential inputs) smaller by ~5x
+
PSI - Jul. 19th, 2005
=
48
Current readout mode
• First implemented in DRS2
• Sampled charge does not leave chip
• Current readout less sensitive to cross-talk etc.
I
Vin
R
Vout
read
write
...
C
PSI - Jul. 19th, 2005
I = c1 * Vin + c2 * Vin * kT
49
Temperature Dependence
Vout vs. Temperature
1.05
Tc ~ 1.4 % / ºC
1
0.95
Vout [V]
0.9
0.85
y = -0.0139x + 1.3938
0.8
20
25
30
35
40
45
T [º C]
DRS2 has a marked dependence on the temperature
PSI - Jul. 19th, 2005
50
Strategy for Temperature Problem
• Put temperature sensors on boards
• Keep electronics temperature stable
(control air condition with
temperature sensors on electronics
to compensate for day-night cycles)
• Calibrate temperature drifts as much
as possible, expect ~1% accuracy by
using the constant level test pulses
• Design DRS3 with temperature
compensation
Vin
write
C
Matched
Transistors
PSI - Jul. 19th, 2005
Vout
Ib
51
DRS board production
• New mezzanine card by end of July → 192 channels
• Test of mezzanine card in September
• Next mezzanine card production cycle in October →
O(1000) channels
• All channels (~2000 DC, ~800 XE, ~200 TC) before
detectors become ready
• Start design of DRS3 in October
• Replace DRS2 by DRS3 in the second half of 2006
PSI - Jul. 19th, 2005
52
DRS3 Design
New DRS3 design:
– All channels differential
– Additional shielding between channels (ground bond
wires)
– Reduced readout time (5x) minimized dead time
– Internal cascading allows for n x 1024 sampling bins
– Intrinsic temperature compensation
PSI - Jul. 19th, 2005
53
DRS (DAQ)
2003
2004
2005
2006
DRS2
DRS2 production
1600 chn
DRS2 test board
DRS3
VME boards
Full System
DRS2
DRS2 production
4000 chn
DRS2 test board
DRS3
4000 chn
VME boards
Full System
PSI - Jul. 19th, 2005
Design
Manufactoring
Replacement
54
Assembly
Test
Milestone
Conclusions
• An electronics integration scheme has been
developed
• Minor details needs to be fixed
• All key electronics elements will be available
before March 06
• A test of the final electronics systems, together
with crates, in magnetic field environment is
planned in autumn
PSI - Jul. 19th, 2005
55
Electronic/DAQ overview
area
LXe
PMT
TC
PMT
216
612
PMT 60 Ramp
Active
Splitter
1:1
1:1
4:1
Active
Splitter
1:1
1:1
4:1
Active
Splitter
1:1
1:1
4:1
DC
1920
DC Pre-Amp
Raw data:
2920 channels
Up to 100 Hz
50% / 10% / 10% occupancy
2kB / waveform
-> 5 x 25 MB/sec.
PSI - Jul. 19th, 2005
trigger
Trigger
2+1 VME
crates
ready
DRS
Board
(32chn)
+ CPU
DRS
Board
(32chn)
+ CPU
6 VME
crates
SIS
SIS
3100
3100
Fitted data:
10 Hz waveform data
-> 1.2 MB/sec
90 Hz ADC / TDC data
-> 0.9 MB/sec
optical
fiber (~20m)
Front-End PCs
Rack – PC (Linux)
Rack – PC (Linux)
Rack – PC (Linux)
Rack – PC (Linux)
Rack – PC (Linux)
Rack – PC (Linux)
Gigabit
Ethernet
Rack – PC (Linux)
Rack – PC (Linux)
Rack – PC (Linux)
Rack – PC (Linux)
On-line farm
storage
56