Transcript 2: Levels of abstraction

ECOE 560
Design Methodologies and Tools for
Software/Hardware Systems
Spring 2004
Serdar Taşıran
Stepwise refinement
 At each level of abstraction, we must:
 analyze the design to determine characteristics of the current
state of the design;
 refine the design to add detail.
 Design: specify and enter
the design intent
Verify:
verify the
correctness of
design and
implementation
Implement:
refine the
design
through all
phases
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ECOE 560, Spring 2004
Successive refinement model
specify
specify
architect
architect
design
design
build
test
initial system
3
build
test
refined system
ECOE 560, Spring 2004
Hardware/software design flow
requirements and
specification
architecture
software design
hardware design
integration
testing
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ECOE 560, Spring 2004
Hierarchical HW/SW flow
spec
spec
spec
architecture
HWSW
architecture
architecture
HW
SW
integrate
integration
integration
test
testtest
system
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detailed
detailed
design
design
hardware
software
ECOE 560, Spring 2004
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ECOE 560, Spring 2004
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ECOE 560, Spring 2004
Outline of today’s lecture
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What is a software/hardware (embedded) system?
Course outline
Design automation methodologies and tools
Levels of abstraction in design descriptions
ECOE 560, Spring 2004
Levels of Abstraction: Hardware
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System level
Register-transfer level (RTL)
Gate level
Transistor level
Layout level
ECOE 560, Spring 2004
System Level
•
Abstract algorithmic description of high-level behavior
– e.g. C-Programming language
Port*
compute_optimal_route_for_packet(Packet_t *packet,
Channel_t *channel)
{
static Queue_t *packet_queue;
packet_queue = add_packet(packet_queue, packet);
...
}
– abstract because it does not contain any implementation details for
timing or data
– efficient to get a compact execution model as first design draft
– difficult to maintain throughout project because no link to
implementation
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ECOE 560, Spring 2004
RTL Level
•
Cycle accurate model “close” to the hardware implementation
– bit-vector data types and operations as abstraction from bit-level
implementation
– sequential constructs (e.g. if - then - else, while loops) to support
modeling of complex control flow
module mark1;
reg [31:0] m[0:8192];
reg [12:0] pc;
reg [31:0] acc;
reg[15:0] ir;
always
begin
ir = m[pc];
if(ir[15:13] == 3b’000)
pc = m[ir[12:0]];
else if (ir[15:13] == 3’b010)
acc = -m[ir[12:0]];
...
end
endmodule
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ECOE 560, Spring 2004
Gate Level
•
Model on finite-state machine level
– models function in Boolean logic using registers and gates
– various delay models for gates and wires
1ns
4ns
3ns
5ns
– in this lecture we will mostly deal with gate level
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ECOE 560, Spring 2004
Transistor Level
•
Model on CMOS transistor level
– depending on application function modeled as resistive switches
• used in functional equivalence checking
– or full differential equations for circuit simulation
• used in detailed timing analysis
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ECOE 560, Spring 2004
Layout Level
•
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Transistors and wires are laid out as polygons in different
technology layers such as diffusion, poly-silicon, metal, etc.
ECOE 560, Spring 2004
Levels of Abstraction: Software
 Specification: Behavioral (UML diagrams, statecharts,
algorithm pseudocode)
 Architecture: Structural (UML), SystemC
 Implementation:
 High-level language
 Assembly
 Executable (binary)
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ECOE 560, Spring 2004
Data flow graph
x = a + b;
y = c - d;
a
b
c
d
z = x * y;
y1 = b + d;
single assignment form
+
-
y
x
*
z
DFG
+
y1
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Control-data flow graph
CDFG: represents control and data.
Uses data flow graphs as components.
Two types of nodes:

decision;

data flow.
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CDFG example
if (cond1) bb1();
T
cond1
else bb2();
bb1()
F
bb3();
switch (test1) {
bb2()
case c1: bb4(); break;
case c2: bb5(); break;
bb3()
case c3: bb6(); break;
}
c1
c3
test1
c2
bb4()
bb5()
bb6()
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Course Outline
 System design flow
 Modeling, specifying, and representing systems:
 Description languages for design specifications and implementations
 Modeling formalisms: Models of computation and concurrency
 Fundamentals:
Boolean algebras, functions, relations. Propositional logic, first-order logic. Temporal
logics.
 Hardware implementation (component) technologies:
CPUs, ASICs, FPGAs, DSPs, IP blocks, I/O components, networks, buses, on-chip
communication networks, reconfigurable platforms.
 Software implementation (component) technologies:
Operating systems, real-time operating systems, inter-process communication,
scheduling.
 Analysis, verification, testing: Functionality.
Design and implementation verification. Simulation, emulation, formal verification.
 Analysis, verification, testing: Performance and timing.
Timing analysis and verification of hardware and software. Performance evaluation
and estimation.
 Analysis, verification, testing: Power.
Power analysis, optimization of hardware and software. Power minimization
techniques.
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System partitioning, architecture exploration.
Hardware synthesis.
Software synthesis
Interface design and synthesis
ECOE 560, Spring 2004