Transcript CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID

CA-BIST for Asynchronous Circuits:
A Case Study on the RAPPID Pentium
R
Pro Instruction Length Decoder
Marly Roncken, Ken Stevens, Shai Rotem - Intel Corporation
Rajesh Pendurkar - Sun Microsystems
ASYNC’00 / MR
Parimal Pal Chaudhuri - Bengal Engineering College
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RAPPID
Revolving Asynchronous Pentium
R
Processor Instruction-length Decoder
RAPPID
Pentium II
(Processor Core)
Throughput [instr/nsec]
RAPPID
3.5
1.2
0
2
4
Deschutes
Latency [nsec]
2.1
5
0
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2
4
6
3.1 x 3.5 mm
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Baseline for Case Study

RAPPID = High-Speed Proof-of-Concept

synchronous basis
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0.25 micron CMOS static + domino library
self-timed addition: Relative Timing

from handshake causality

to relative assumptions
Testability study started afterwards

no DfT in core design - but some debug features

considered a major risk in performance + fault coverage
Wanted: non-invasive test approach

outside RAPPID core

low performance penalty

no re-design
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Objectives
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Achieve 95% fault coverage with non-scan BIST
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
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look for fast ways to tune BIST to RAPPID
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beyond pseudo-random testing
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use HDM coverage metric : min-terms in Length Decode PLA
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follow design architecture : replication
use Cellular Automata BIST
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wider behavior than LFSR solutions
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expert in-house
Analyze testability impact of Relative Timing
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take BIST solution - analyze undetected stuck-at faults
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manageable
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in-focus
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high fault coverage leaves relatively few undetected faults
HDM coverage metric uncovers implementation-specific faults
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Outline
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Part I
CA-BIST solution for RAPPID
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RAPPID interface and design hooks
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CA-BIST architecture + algorithm + costs
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CA test generation engine
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bootstrapped test expansion
Part II
Stuck-at fault analysis for Relative Timing
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fault coverage distribution
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benign and suspicious escapees
Conclusion
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CA-BIST - starting point
RAPPID
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CA-BIST - starting point
CATPG
CARE
RAPPID
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RAPPID - core Architecture
16x replication
used in CATPG
Byte
Row 0
Tag Unit
Row 1
Tag Unit
Tag Unit
Tag Unit
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3 4
5
6 7 8
9 10 11 12 13 14 15
optimal balance
(common instr)
Length
Decode
Row 2
CTRL
1 2
Byte
Latch
Row 3
Byte Unit
Column 0
Decode and Steer Unit
720 MHz
3.6 GHz
Crossbar Switch
900 MHz
Crossbar Switch
Output Buffer
Crossbar Switch
Output Buffer
Crossbar Switch
Outputs shared
Output Buffer
in CARE
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RAPPID - input FIFO
RAPPID
CATPG

interface to the tester
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interface to RAPPID
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data bytes in circular scan
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share circular scan
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branch status register / byte
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at-speed performance testing
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from external Branch Target Buffer
16/32-bit instruction modes
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global setting
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instruction based local setting
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to bootstrap test generation
share 3-bit status register
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direct access via test circuit BRT
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2-byte-instruction based setting
share 16/32 global setting
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test patterns cover local setting
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CA-BIST - interfacing RAPPID
CATPG
CA
CARE
RAPPID
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One for All: CA test engine
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Generate initial fillings for 16 instruction bytes
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11-bit D1*CA + dual version
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11 state bits - take first 8 bits as test instruction byte
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48 pairs of state components with cycle length 16
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no LFSR implementation
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D1*CA component Pair
16x S0-S0 cycle
=16 FIFO fillings
Normal
S0
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Dual
?
16x S1-S1 cycle
=16 FIFO fillings
S1
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Traversal algorithm
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Step 1
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S0 := normal cyclic state := S2
Step 2
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S1 := S0 with inverted MSB
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run S1-S1 dual cycle
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use state outputs as test bytes
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Step 3
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S0 := next normal state after S1
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run S0-S0 normal cycle
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use state outputs as test bytes
Step 4
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STOP if ( S0=S2 ) else Step 2
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All for One: test expansion
design replication
used in CATPG
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Circular scan + Bootstrap Algorithm (256x)
Step 1: run Traversal Algorithm for next FIFO filling
Step 2: 128x ( left-rotate FIFO by 1 bit + test RAPPID )
Step 3: repeat Step 2 with right-rotate
Step 4: STOP if end-of-Traversal-Algorithm else Step 1
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ASYNC’00 / MR
Add Test circuitry to close test gaps
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HDM coverage revealed 66-0F gap for long instruction
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extra Test Circuitry to circulate 66-0F in test set
Test operation modes (4x)
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16/32 bit instruction modes
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BRT to test branch instructions
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660F to cover remaining test gap
1024 x 32 tests
100% coverage
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CA-BIST solution
CATPG
CA
CARE
RAPPID
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Costs
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performance
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latency
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CATPG
1 gate delay (shared scan)
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CARE
negligible output load+delay
throughput
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CATPG + CARE
0%
off critical path
area
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5%
from schematics
5% (including circular scan)
fault coverage
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for HDM
100% PLA min-terms
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at switch level
94% testable stuck-at faults
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Stuck-at fault Analysis
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120,000 transistors
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static + domino gates
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pass + reset transistors
Column 0
Decode and Steer Unit
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switch-level fault analysis
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COSMOS
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stuck-at input + output
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simulated for full RAPPID
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only injected in 1 column-row
Tag Unit
Crossbar Switch
9%
5%
5%
excellent ATPG
candidates
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81%
Detected
Unexercised
Benign
Suspicious
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Benign & Suspicious Escapees
full keeper
for 0 & 1
half keeper
for 1
only
footed protection
no foot
set-reset overlap ( c d )
for pulse-d evaluations
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Domino Escapees
@0
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pulse narrowing
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fast slow
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d fights keeper (weak)
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push-out of z:=0
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slightly deteriorated 0
keeper helps reset c
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push-forward of z:=1
floating gate output
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z floats when neither set-reset
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relative timing matters
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benign
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wide evaluation pulse
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d stays valid during evaluation
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redundant n-transistor in keeper
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test at low speed or frequency
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within specification range
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increases test application costs
noise sensitive
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fast reset OK, slow NOT OK
suspicious
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@1
test for realistic noise conditions
similar for clocked design
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Pulse domino Escapees
@0
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pulse narrowing
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d fights keeper (weak)
suspicious
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push-out of z:=0
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d0d1d2 reset during evaluation
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slightly deteriorated 0
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required for un-footed gate
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crucial n-transistor in keeper
keeper helps reset c
push-forward of z:=1
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benign
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wide evaluation pulse
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d stays valid during evaluation
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redundant n-transistor in keeper
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output pulse shrinks >50%
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from 7 gate delays ( c loop )
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to 3 gate delays ( d2 loop )
noise sensitive
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small input pulse
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noise can make pulse narrower
similar for self-reset clocks
in `synchronous’ pulse logic
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Conclusion
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Testability is no excuse
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to avoid asynchronous + clocked high-performance
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similar fault effects for RAPPID and clocked domino
CA-BIST without scan works for RAPPID
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non-invasive with low performance + area penalty
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covers 94% of testable faults
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remaining 6% relate to missing data operands
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suitable minority for tailored ATPG + off-chip testing
… and BIST tuning
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RAPPID column replication tuned test expansion
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Current
focus
not always so obvious
HDM coverage metric tuned CATPG solution
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ASYNC’00 / MR
… but missed 5% potentially catastrophic timing related faults
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