Transcript COMP3221: Microprocessors and Embedded Systems

COMP3221: Microprocessors and
Embedded Systems
Lecture 23: Memory Systems (I)
http://www.cse.unsw.edu.au/~cs3221
Lecturer: Hui Wu
Session 2, 2005
Overview
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Memory System Hierarchy
RAM, ROM, EPROM, EEPROM and FLASH
COMP3221/9221: Microprocessors
and Embedded Systems
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Memory System Hierarchy
Processor
Control
Off-chip
memory
(RAM,
ROM)
Datapath
Registers
Fastest but
most
expensive
Decreasing
speed and
Increasing
cost
size
Cache or
On-chip
memory
Auxiliary
storage
(hard disk,
floppy
disk,
CDROM)
Slowest
and
cheapest
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Memory System Hierarchy
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Registers
 Fastest but most expensive.
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Cache
 Slower than registers but bigger size.
 Managed by hardware and therefore typically invisible to
programmers.
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On-chip memory (RAM and ROM)
 An alternative for cache.
 Managed by the software.
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External memory (RAM and ROM)
 Slower than on-chip memory but bigger size.
•
Auxiliary storage (Hard disk, floppy disk, CDROM)
 Much slower than external memory but much bigger size.
 Non-volatile i.e. data exists after the power is switched off.
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Computer Types and Memory
Maps
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General purpose computer systems
 Programs and data (including OS) are stored on the auxiliary storage
(typically hard disk).
 A large amount of RAM to store programs and data.
 When executed, programs are loaded from disk to RAM by OS.
 ROM to store boot-up code and low-level system I/O drivers.
•
Embedded systems
 Typically no auxiliary storage.
 Program and constants are stored in ROM or non-volatile memory
such as flash.
 Data are stored in RAM.

Program could be copied from ROM to RAM to increase the execution
speed.
 On-chip memory is preferred to cache due to its low power
consumption.
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Computer Types and Memory
Maps (Cont.)
Low Memory
Address
High Memory
Address
Area of RAM
reserved for OS
RAM
Application
Programs
ROM
BIOS and bootup code
A general-purpose computer memory map
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Computer Types and Memory
Maps (Cont.)
Low Memory
Address
RAM
Enough RAM for
variables and stack
None
High Memory
Address
ROM
Enough ROM for
application programs
and possibly OS
An embedded system memory map
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Semiconductor RAM
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Memories are semiconductor integrated circuits.
A RAM (Random Access Memory) chip consists of an
array of memory cells, a decoder for addressing a
particular cell, and signals to control the direction of data
flow.
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An Example Semiconductor RAM
5-Bit
Row
Address
5
5-to-32
Row
Address
Decoder
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32×32-bit
RAM Array
32
5-Bit
Column
Address
5
32
32-1 Multiplexer
CE
32-1 Demultiplexer
R/W
Di
Do
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An Example Semiconductor RAM
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The CE signal (chip enable, or sometimes CS, chip select)
is derived by decoding the rest of address bus.
R/W controls whether the memory cell is being read from
or written to.
Di and Do are separate data-in and data-out pins.

Some chip has a single data I/O pin.
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Static Memory Cells
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A static memory cell is a flip-flop.
The transistors could be bipolar or MOS devices.
The following figure shows a typical static memory cell.
C
3.5 V
R1
D1
R2
2.5 V
0V
Q1
A
C´
R1´
A´
D1´
R2´
Q1´
ROW_SELECT
COLUMN LINES
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Static Memory Cells
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The bipolar flip-flop works as follows
 Assume the ROW_SELECT is high (2.5 volts) and that transistor
Q1 is on. Current flows through R1 and R2, which are chosen to
make the voltage at point A higher than the column line C. Q1 is
off, making the voltage at point A higher than the column line C.
Thus, when the row is not selected, the diodes D1 and D1 isolate
the cell from from the column lines C and C. When the cell is read,
ROW_SELECT is asserted (it now is 0 volt), point A becomes
lower than C, and current flows in diode D1 from column line C.
This current could signify a logic one stored in the cell. A logic
zero is stored by turning Q1 off and Q1 on. Now, when
ROW_SELECT is asserted , the C column line will not have
current flow while C will. Writing into the cell involves asserting
the ROW_SELECT and driving either C or C to set Q1 or Q1
depending on whether zero or one is to be stored.
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Dynamic Memory Cells
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•
A dynamic cell is a capacitor where absence or presence of
charge denotes a stored one or zero.
The following figure shows a typical dynamic memory cell.
 The MOS capacitor can be written to by activating the row, or
word, line to turn the MOS transistor on and charge the capacitor
through the column, or bit, line.
 The cell can be read by turning the transistor on and sensing a
voltage on the column.
Row or
Word Line
MOS
Transistor
MOS
Capacitor
Column or
Bit Line
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Dynamic Memory Cells (Cont.)
•
A problem with dynamic cell is that the charge stored on the
capacitor leaks away through the substrate.
 Thus, the dynamic memory must be refreshed at periodic intervals
by activating ROW_SELECT line while holding all column lines at
a particular voltage level.
 All cells in the row can have the capacitor’s charge (or lack of
charge) refreshed at once.
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Static Memory
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Static RAM, or SRAM, consists of array of flip-flops.
Has lower density and thus lower storage capability than
dynamic RAM.
Simpler to use than dynamic RAM
Does not need to refreshed like DRAM.
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Static Memory (Cont.)
Logic block diagram of a typical SRAM
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Dynamic Memory
RAS
CAS
CONTROL &
CLOCKS
FRESH CONTROL &
ADDRESS COUNTER
W
COLUMN DECODER
DATA IN
BUFFER
D
DATA OUT
BUFFER
Q
SENSE AMPS & I/O GATINGS
ADDRESS COUNTER
REFRESH CONTROL&
MEMORY ARRAY
1,048,567 CELLS
Vcc
Vss
Intel 1M×1-bit DRAM
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Dynamic Memory (Cont.)
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The DRAM chip has 10 bits, separate data-in and data-out
pins, a write enable (w), and two other control signals: RAS
(row address strobe) and CAS (column address strobe).
 RAS and CAS control the multiplexing of the two 10-bit address
fields that make up the full 20-bit address required for 1M bits.
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DRAM Refresh
The DRAM memory cell requires periodic refresh operation.
There are several refresh methods.
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RAS-only refresh: This is the most common method of refresh. The
row addresses are strobed by asserting RAS while CAS is held
high. The cycle must be repeated for every row address.
CAS-before-RAS refresh: CAS-before-RAS eliminates the need
for external refresh addresses. If CAS is held low, a specified time
before RAS is asserted, on-chip refresh circuitry automatically
furnishes the refresh address. This method takes slightly longer
time than RAS-only method.
Hidden refresh:This refresh is done while maintaining the latest
valid data at the output and extending CAS and cycling RAS.
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Pseudostatic RAM
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A memory that combines the high storage capability of
DRAM and ease of use of SRAM is pheudostatic RAM.
It uses DRAM cells and includes on-chip refresh circuitry so
that it appears to the user as SRAM.
Some care must be taken to avoid a conflict when the system
attempts to access the memory while an internal refresh is
being done. Two approaches may be included in the design of
the chip to solve this problem:
 In the first approach, a separate pin may be included to tell the RAM
when it can execute a refresh cycle without conflicting with an
external access request. External logic can pusle this input to refresh
the chip.
 In the second approach, a “ready” or “wait” output from the RAM
may be used for handshaking in a system where “wait state” can be
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generated.
ROM Memory
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There are various types of ROM memory chips.
 Mask programmable ROM are programmed during the
manufacturing stage and cannot be programmed by user.
 Other ROM devices are field programmable and may be
programmed by the user. These care called programmable read only
memories., and include UV-erasable PROMs (EPROMs), one-time
programmable (OTP) EPROMs, and fusible-link PROMs.



EPROMs are electrically programmable are erased by irradiating the
chip through a quartz window with ultraviolet (UV) light.
An OTP EPROM is an EPROM without the window so that once
programmed, it cannot be erased.
Another type of programmable read only memory is the electrically
erasable PROM (EEPROM), which can be programmed and erased
while in use.
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ROM Memory Cells
Bit Line
Word
Line
Gate
Bit Line
No Gate
Bit Line
Gate
ROM cell
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ROM Memory Cells (Cont.)
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The ROM memory cell is simply a wire or connection made
or not made in the programming process.
The binary information is represented by the presence or
absence of the gate on the MOS transistor.
Activating the word line puts a one or zero on the bit line.
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EPROM Memory Cells
UV Light to Erase
Quartz Window
Drain
Source
SiO2
Filed Oxide
n+
Electrons injected
to program
Field Oxide
n+
Si Floating Gate
p-Substrate
EPROM Cell
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EPROM Memory Cells (Cont.)
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The EPROM cell is a MOS transistor without a connection to
the gate.
To program the EPROM, the chip is placed into a PROM
programmer and during the programming cycle, the address
and data are sent to the chip and the programming voltage is
applied. To change the state of the gate, electrons are either
injected by an avalanche mechanism into the silicon floating
gate or not. This after the programming, the channel between
the source and and the drain either conducts or does not.
If the chip needs to be erased, it must be placed into the
PROM eraser. The ultraviolet light irradiated from the PROM
eraser disperses any charge stored in the floating gate back
into the substrate and erases the memory.
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EEPROM Memory Cells
Control Gate
Drain
Source
SiO2
Filed Oxide
n+
Electrons injected
to program
Field Oxide
n+
Si Floating Gate
p-Substrate
EEPROM Cell
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EEPROM Memory
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The EEPROM is a further development of the EPROM.
A second polysilicon gate, called the control gate, is added
above the floating gate.
A control voltage may be applied to the gate to program and
erase the cell by injecting or disperse electrons in the floating
gate.
EEPROM can be programmed and erased without removing
the chip from the circuit in use.
The time required to write is longer than a comparable RAM
chip.
There is a maximum number of times it can be programmed
(the industry standard as of 1993 is 10,000 program/erase
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cycles).
FLASH Memory
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Similar to the EEPROM.
Its drawback is that the entire memory or page must be erased
where single locations can be erased and reprogrammed in
the EEPROM devices.
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Reading
1. Chapter 9: Computer Memories. Microcontrollers and
Microcomputers by Fredrick M. Cady
2. http://computer.howstuffworks.com/computer-memory.htm
COMP3221/9221: Microprocessors
and Embedded Systems
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