Transcript Document

Presentation #2: Rijndael Encryption
Team W1
Design Manager: Rebecca Miller
1. Bobby Colyer (W11)
2. Jeffrey Kuo (W12)
3. Myron Kwai (W13)
4. Shirlene Lim (W14)
Stage II:
26th January 2004
ARCHITECTURE PROPOSAL
Overall Project Objective:
Implement the new AES Rijndael algorithm on chip
18-525 Integrated Circuit Design Project
Status
 Design Proposal
 Project Chosen - Alternatives Studied and Eliminated
 Verilog Obtained
 Architecture Proposal
 Final Algorithm Description
 Mapping of algorithm to hardware (block diagram)
 Behavioral Verilog simulation and test bench
 To be Done
 Gate Level Design
 Schematic Design
 Floorplan
 Layout
 Simulations/Optimizations
 Everything else…
18-525 Integrated Circuit Design Project
Design Decisions
PREVIOUS PROBLEMS
Cut down 128-bit design to 32-bit design
Different implementations of Rijndael
Too many transistors / design too big
Parallel design – more transistors but faster?
 DECISIONS
 Decided/changed 128-bit design to 32-bit design
 32-bit design but implementing full SBOX
 Decided to stick with the Rijndael implementation that incorporated a
multiplier instead of just XORing the values.
 Increases complexity of design
 Too many transistors/design too big – will further optimize design
 Implementation of ROM instead of SRAM or registers
 Decided to stick with parallelism
 Two different blocks
18-525 Integrated Circuit Design Project
Implementation Revised
Previous
Implementation
Removed last
MixColumn Function
Replaced with AddRoundKey
in accordance to new
implementation chosen
18-525 Integrated Circuit Design Project
Final Algorithm Description
INITIAL ROUND
KeyAdd
Cipher Key
Round Key
Plain Text
REPEAT 9 ROUNDS
ByteSub
ShiftRow
MixColumn
KeyAdd
Cipher Text
KeyAdd
ShiftRow
ByteSub
FINAL ROUND
RoundKey
18-525 Integrated Circuit Design Project
Mapping Algorithm to Hardware
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
ROM
BLOCK
BLOCK
BLOCK
BLOCK
BLOCK
New Implementation: 10-stage Pipelined Design
 Increased throughput
 Increased speed
LOOKS SIMPLE BUT…
Timing issues…
Proposed 2 S-BOX as part of ROM
10 Blocks with 5 Blocks per S-BOX
Each Block accessing S-BOX 4 times, total of 20 per S-BOX per clock
18-525 Integrated Circuit Design Project
Block Diagrams (cont’d)
Cipher Key
Control
logic
ROM
RCON
Multiplier
Multiplier
+
ONE “BLOCK”
18-525 Integrated Circuit Design Project
Plain
Text
FIPS Test Vectors
Using FIPS Test
Vectors for Verilog
Simulation Verification
FIPS – Federal
Information
Processing
Standards
18-525 Integrated Circuit Design Project
Verilog Test Bench
18-525 Integrated Circuit Design Project
Verilog Simulation (VSim)
18-525 Integrated Circuit Design Project
Verification of Output
18-525 Integrated Circuit Design Project
Previous Transistor Count
(Assuming 32-bit Implementation)




~256 Registers
XORs
Inverters/Buffers
SBOX
 Registers
 Key Schedule
 XORs
 Shifters (Hardcoded – Just routing wires)
 Muxes
Total:
18-525 Integrated Circuit Design Project
~3500
~1200
~500
~12000
~100
0
~8000
~25300
New Transistor Count
(Assuming 32-bit Implementation)







SBOX – Part of ROM (2)
Control Logic (2)
Multiplier (20)
Adders (10)
RCON – Part of ROM (1)
Buffering/MUXes
XORs
~4000
~4000
~12000
~2500
~1000
~2000
~5000
Total:
~30500
18-525 Integrated Circuit Design Project
Problems
 Timing issues
 Clock skew
 Pipelined design

Each S-BOX being accessed by several different stages
 Research on clock-tree implementations
 So we can organize our 10 blocks optimally
 Transistor sizing
 Transistor sizing affects efficiency of SBOX access
18-525 Integrated Circuit Design Project
Questions?
18-525 Integrated Circuit Design Project