Transcript Characterization Integration

Carrier Mobility and Velocity

Mobility - the ease at which a carrier
(electron or hole) moves in a
semiconductor
– Symbol: mn for electrons and mp for holes

Drift velocity – the speed at which a
carrier moves in a crystal when an electric
field is present
– For electrons: vd = mn E
– For holes:
vd = mp E
L
H
W
Va
Va
Resistance
L
L
R
 
WH
A
Resistivity and Conductivity

Fundamental material properties
1
1


q m n no  m p po  q m n  m p ni

1

Resistivity
n-type semiconductor
1

q m n no  m p po 

1

ni 

q m n N d  m p

N
d 

1

qm n N d
2
p-type semiconductor
1

qm n no  m p po 

1
 ni 2

q m n
 m p N a 
 Na

1

qm p N a
Drift Currents
Va
Va
I

R

L 
1

A  q m n no  m p po  
Va
I
Aqm n no  m p po 
L
Va
E
L
I  Aqm n no  m p po E
Diffusion

When there are changes in the
concentration of electrons and/or holes
along a piece of semiconductor
– the Coulombic repulsion of the carriers force
the carriers to flow towards the region with a
lower concentration.
Diffusion Currents
I diffn
A
I diff p
A
I diff
A
 J diffn
dno
 qDnno  qDn
dx
 J diffp
dpo
 qD p po   qD p
dx
 J diffn  J diffp  q Dnno  D p po 
Relationship between Diffusivity
and Mobility
Dn
kT

mn
q
Dp
kT

mp
q
Mobility vs. Dopant Concentration
in Silicon
http://www.ioffe.ru/SVA/NSM/Semicond/Si/electric.html#Hall
Wafer Characterization

X-ray Diffraction
– Crystal Orientation

Van der Pauw or Hall Measurements
– Resistivity
– Mobility

Four Point Probe
– Resisitivity

Hot Point Probe
– n or p-type material
Van der Pauw
Four equidistant Ohmic
contacts
 Contacts are small in
area
 Current is injected
across the diagonal
 Voltage is measured
across the other
Top view of Van der Pauw sample
diagonal
http://www.eeel.nist.gov/812/meas.htm#geom

Calculation

Resistance is determined with and without a
magnetic field applied perpendicular to the
sample.
t R13, 24
mH 
B 
t R12,34  R23,14

F
ln 2
2
F is a correction factor that takes
into account the geometric shape
of the sample.
Hall Measurement
http://www.sp.phy.cam.ac.uk/SPWeb/research/QHE.html

See http://www.eeel.nist.gov/812/hall.html for a
more complete explanation
Calculation

Measurement of resistance is made while a
magnetic field is applied perpendicular to the
surface of the Hall sample.
– The force applied causes a build-up of carriers along
the sidewall of the sample
 The magnitude of this buildup is also a function of the
mobility of the carriers
RH
RH A
mH 


RL L
where A is the cross-sectional area.
Four Point Probe

Probe tips must make
an Ohmic contact
– Useful for Si
– Not most compound
semiconductors
V
  2S when t  S
I
t V

when t  S
ln 2 I
Hot Point Probe

Simple method to determine whether
material is n-type or p-type
– Note that the sign of the Hall voltage, VH, and
on  R13,24 in the Van der Pauw measurement
also provide information on doping.
Visual Information on Crystal
Orientation and Doping
Used on wafers that are less than 200 mm in diameter (8 inches)
Key Inventions

Three discoveries made integrated circuits
possible:
– Invention of the transistor
(1949 by Brattain, Bardeen, and Schockley;
Nobel prize 1972)
– Development of planar transistor technology
(1959 by Bob Noyce and Jean Hoerni; Noyce
was a founder of Intel)
– Invention of integrated circuit
(1959 by Kilby; Nobel prize 2000)
The First Transistor

The first transistor, a
point contact pnp Ge
device, was invented in
1947 by John Bardeen,
Walter Brattain, and
William Shockley. They
received the Nobel Prize
in physics in 1956.
The first integrated circuit

The first integrated circuit
was invented by Jack Kilby of
TI. He received the Nobel
Prize in 2000.
Levels of Integrated Circuits

Small Scale Integration (SSI)
 1-10 transistors

Medium Scale Integration (MSI)
 up to 100 transistors

Large Scale Integration (LSI)
 up to 10,000 transistors

Very Large Scale Integration (VLSI)
 millions of transistors




Ultra Large Scale Integration
Wafer Scale Integration
System on a Chip (SOC)
3D IC
Increase in Complexity of Chips
Moore’s Law

Gordon Moore observed (1965) that the
number of transistors on a Si chip was
doubling every year. Later, revised this to
every 18 months.
– This cannot continue forever; when
components reach size of atoms, the physics
changes.
– Currently, there is no known solution.
Historical Trends
of Minimum Feature Size
Minimum
Feature Size:
13% reduction
each year;
recently closer
to 10%.
Projections from 1997 Roadmap

The fundamental assumption is that Si will be
the material of choice and that Moore’s law
will apply until 2012
Scaling as a Function of Cycle Time
S  0.7
CARR (T )  S

1
2 2T
1
S is the minimum feature size
T is the cycle time
CARR is the Compound Annual Reduction Rate
On average, the minimum feature size decreases by
10-13%/year. Currently at 45 or 32 nm node
Where are we today?
Semiconductor Trends

Overall chip size has been increasing by
16%/year over past 35 years
– Recently 6.3%/year for microprocessors and
12%/year for DRAM
– Major limitation is the number of pads that can be
placed on the chip to get signals in and out

Trends are now projected by the SIA national
Technology Roadmap for Semiconductors
 Current version is called International Technology Roadmap
for Semiconductors
Cost of Designing a Chip

The cost of designing a chip has increased
with the complexity of the chip.
– Initially, the cost seemed to follows Moore’s
law—the cost doubled every time the
complexity doubled.
– The controlling factor was the development of
CAD and modeling software.
Cleanrooms
Federal
Standard
TC 209
ISO
1
2
1
3
10
4
100
5
1,000
6
10,000
7
100,000
8
9
First Line of Protection: Bunny Suits
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