Transcript EECS 40

Donovan T. Lee
Integrated Circuit Technology
EE40
6 August 2008
Donovan T. Lee
Integrated Circuit Fabrication
Goal:
Mass fabrication (i.e. simultaneous fabrication) of many
“chips”, each a circuit (e.g. a microprocessor or memory
chip) containing millions or billions of transistors
Methods for Top Down processing:
1. Addition of material
2. Subtraction of unwanted material
3. Thermal/Doping modification of material
Analogous to making Gingerbread men… yeah.
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Still in Infancy: Bottom-up Processing
Cheap electronics
Organic Printed Electronics – Process is serial (slow) and
resolution is poor
High-performance transistors
Catalyzed Growth – Nanotubes/Nanowires hard to place
and grow in the desired direction.
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Standard Materials Set
•
•
•
•
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Si substrate – selectively doped in various regions
SiO2 insulator – MOST IMPORTANT component
Polycrystalline silicon – used for the gate electrodes
Metal contacts and wiring
Si Substrates (Wafers)
Why are wafers round?
We pull crystalline-Si out of hot ingots, starting with a seed crystal.
Crystalline-Si exhibits the best electronic properties for transistors.
300 mm
Typical wafer cost: $50 (!!!)
Sizes: 150 mm, 200 mm, 300 mm diameter
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“notch” indicates
crystal orientation
Doping
Makes the Silicon N-type or P-type
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Adding Dopants into Si
Suppose we have a wafer of Si which is p-type and we want to
change the surface to n-type. The way in which this is done is by
ion implantation. Dopant ions are shot out of an “ion gun” called
an ion implanter, into the surface of the wafer.
As+ or P+ or B+ ions
Eaton HE3
High-Energy
Implanter,
showing the
ion beam
hitting the
end-station
+
+
+
+
+
+
SiO2
x
Si
Typical implant energies are in the range 1-200 keV. After the ion
implantation, the wafers are heated to a high temperature (~1000oC).
This “annealing” step heals the damage and causes the implanted
dopant atoms to move into substitutional lattice sites.
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Ion Implanter
e.g. AsH3 gaseous source
As+, AsH+, H+, AsH2+
Ion
source

analyzer magnet
F = q( v B )
ion beam
Energy: 1 to 200 keV
Dose: 1011 to1016/cm2
Inaccuracy of dose: <0.5%
Nonuniformity: <1%
Throughput: ~60 wafers/hr
resolving aperture
accelerator
translational
motion
As+
wafer
spinning wafer
holder
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Dopant Diffusion
• The implanted depth-profile of dopant atoms is peaked.
dopant atom
concentration
(logarithmic
scale)
as-implanted
profile
depth, x
• In order to achieve a more uniform dopant profile, hightemperature annealing is used to diffuse the dopants
• Dopants can also be directly introduced into the surface of
a wafer by diffusion (rather than by ion implantation) from
a dopant-containing ambient or doped solid source
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Annealing
Fixes the damage caused by ion
implantation.
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Rapid Thermal Annealing (RTA)
Sub-micron MOSFETs need ultra-shallow junctions (xj<50 nm)
 Dopant diffusion during “activation” anneal must be minimized
 Short annealing time (<1 min.) at high temperature is required
• Ordinary furnaces (e.g. used for thermal oxidation and CVD)
heat and cool wafers at a slow rate (<50oC per minute)
• Special annealing tools have been developed to enable
much faster temperature ramping, and precise control of
annealing time
– ramp rates as fast as 200oC/second
– anneal times as short as 0.5 second
– typically single-wafer process chamber:
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Rapid Thermal Annealing Tools
•
There are 2 types of RTA systems:
1. Furnace-based
•
steady heat source + fast mechanical wafer transport
2. Lamp-based
•
stationary wafer + time-varying optical output from lamp(s)
Furnace RTA
Lamp RTA
A.T. Fiory, Proc. RTP2000
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Film Growth
Allows formation of high-quality films
(usually SiO2) necessary for low
leakage.
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Formation of Insulating Films
•
The favored insulator is pure silicon dioxide (SiO2).
•
A SiO2 film can be formed by one of two methods:
1. Oxidation of Si at high temperature in O2 or steam ambient
2. Deposition of a silicon dioxide film
Applied Materials lowpressure chemical-vapor
deposition (CVD) chamber
ASM A412
batch
oxidation
furnace
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Thermal Oxidation
Si  O2  SiO2 or
Si  2H 2O  SiO2  2H 2
“dry” oxidation
• Temperature range:
 700oC to 1100oC
• Process:
 O2 or H2O diffuses through
SiO2 and reacts with Si at the
interface to form more SiO2
• 1 mm of SiO2 formed
consumes ~0.5 mm of Si
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“wet” oxidation
oxide
thickness
 t
t
time, t
Example: Thermal Oxidation of Silicon
Silicon wafer, 100 mm thick
Thermal oxidation grows SiO2 on Si, but it consumes Si, so
the wafer gets thinner. Suppose we grow 1 mm of oxide:
101mm
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99mm
99 mm thick Si, with 1 mm SiO2 all around
 total thickness = 101 mm
Oxidation Rate Dependence on Thickness
• The thermal oxidation rate slows with oxide thickness.
Consider a Si wafer with a patterned oxide layer:
SiO2 thickness = 1 mm
Si
Now suppose we grow 0.1 mm of SiO2:
Note the 0.04mm step in the Si surface!
SiO2 thickness = 1.02 mm
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SiO2 thickness = 0.1 mm
Selective Oxidation Techniques
Window Oxidation
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Local Oxidation (LOCOS)
Deposition
Allows you to put down conformal films that
cannot be grown from the substrate.
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Chemical Vapor Deposition (CVD)
of SiO2
Si(C2 H 5O) 4  2H 2O  SiO2  4C2 H 6O
or SiH 4  O2  SiO2  2H 2 “LTO”
“TEOS”
• Temperature range:
 350oC to 450oC for silane
 ~700oC for TEOS
• Process:
 Precursor gases dissociate at
the wafer surface to form SiO2
 No Si on the wafer surface is
consumed
• Film thickness is controlled by
the deposition time
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oxide
thickness
t
time, t
Conformality
CVD Properties:
•Can be deposited on top of anything.
•Can follow ups & downs (topography) of pre-existing layers
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Lithographic Patterning
Film-camera-like process that lets
you define shapes in your thin films.
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Patterning the Layers
Planar processing consists of a sequence of
additive and subtractive steps with lateral patterning
oxidation
deposition
ion implantation
etching
lithography
Lithography refers to the process of transferring a pattern
to the surface of the wafer
Equipment, materials, and processes needed:
• A mask (for each layer to be patterned) with the desired pattern
• A light-sensitive material (called photoresist) covering the wafer so as
to receive the pattern
• A light source and method of projecting the image of the mask onto the
photoresist (“printer” or “projection stepper” or “projection scanner”)
• A method of “developing” the photoresist, that is selectively removing it
from the regions where it was exposed
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Photoresist Exposure
• A glass mask with a black/clear pattern is used to
expose a wafer coated with ~1 mm thick photoresist
UV light
Mask
Lens
Image of mask
appears here
(3 dark areas,
4 light areas)
photoresist
Si wafer
Mask image is
demagnified by nX
“10X stepper”
“4X stepper”
“1X stepper”
Areas exposed to UV light are susceptible to chemical removal
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Exposure using “Stepper” Tool
field size increases
with technology
generation
scribe line
1
2
wafer
images
Translational
motion
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Commercial Stepper Tool (ASM Lithography)
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Photoresist Development
• Solutions with high pH dissolve the areas which were
exposed to UV light; unexposed areas are not dissolved
Exposed areas of photoresist
Developed photoresist
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Lithography Example
• Mask pattern (on glass plate)
A
A
B
B
• Look at cuts (cross sections)
at various planes
(A-A and B-B)
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“A-A” Cross-Section
The resist is exposed in the ranges 0 < x < 2 mm & 3 < x < 5 mm:
0
1
2
3
4
5
x [mm]
mask
pattern
resist
0
1
2
3
4
5
x [mm]
The resist will dissolve in high pH solutions wherever it was exposed:
resist after
development
0
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1
2
3
4
5
x [mm]
Pattern Transfer by Etching
In order to transfer the photoresist pattern to an underlying film, we need a
“subtractive” process that removes the film, ideally with minimal change in
the pattern and with minimal removal of the underlying material(s)
 Selective etch processes (using plasma or aqueous chemistry)
have been developed for most IC materials
photoresist
First: pattern
photoresist
Si
Next: Etch oxide
Last: strip
resist
SiO2
We have exposed mask pattern,
and developed the resist
oxide etchant …
photoresist is resistant.
etch stops on silicon
(“selective etchant”)
only resist is attacked
Jargon for this entire sequence of process steps: “pattern using XX mask”
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Photolithography
quartz plate
chromium
• 2 types of photoresist:
– positive tone:
portion exposed to light will
be dissolved in developer
solution
– negative tone:
portion exposed to light will
NOT be dissolved in
developer solution
from Atlas of IC Technologies by W. Maly
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Projection Printing Considerations
minimum feature size  lm :
Intel’s Lithography Roadmap
Small lm is desired!
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Depth of Focus
depth of focus  Dz :
Large Dz is desirable.
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Etching
Remove material that you don’t want
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Etching: Ion vs. Wet
from Atlas of IC Technologies by W. Maly
 better control of etched feature sizes
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 better etch selectivity
RIE-based Stringers / Spacers
Leftover material must be removed by overetching
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D’oh! Stringers
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Example Process Flow
CMOS Technology
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CMOS Technology
Challenge: Build both NMOS & PMOS transistors
on a single silicon chip
• NMOSFETs need a p-type substrate
• PMOSFETs need an n-type substrate
 Requires extra process steps!
oxide
p+
p+
n+
n+
p-well
n-type Si
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Conceptual CMOS Process Flow
n-type wafer
*Create “p-well”
oxide
p+
p+
n+
n+
p-well
n-type Si
Grow thick oxide
*Remove thick oxide in transistor areas (“active region”)
Grow gate oxide
Deposit & *pattern poly-Si gate electrodes
*Dope n channel source and drains (need to protect PMOS areas)
*Dope p-channel source and drains (need to protect NMOS areas)
Deposit insulating layer (oxide)
*Open contact holes
→ At least 3 more masks, as
compared to NMOS process
Deposit and *pattern metal interconnects
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Additional Process Steps Required for
CMOS
1. Well Formation
Top view of p-well mask
(dark field)
Cross-sectional view of wafer
boron
SiO2
p-well
n-type Si
•
Before transistor fabrication, we must perform the
following process steps:
1. grow oxide layer; pattern oxide using p-well mask
2. implant phosphorus; anneal to form deep p-type
regions
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2. Masking the Source/Drain Implants
“Select p-channel”
We must protect the n-channel devices during the
boron implantation step, and
“Select n-channel”
We must protect the p-channel devices during the
arsenic implantation step
Example: Select p-channel
boron
photoresist
oxide
p+
p+
n+
n+
p-well
n-type Si
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Forming Body Contacts
Modify oxide mask and “select” masks:
1. Open holes in original oxide layer, for body contacts
2. Include openings in select masks, to dope these regions
oxide
n+
p+
p+
n+
n+
p-well
n-type Si
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p+
Select Masks
N-select:
oxide
n+
n+
n+
p-well
n-type Si
P-select:
oxide
n+
p+
p+
n+
n+
p-well
n-type Si
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p+
Example MEMS Flow
Micro Electro Mechanical Systems
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MEMS Switch
Source
Drain
Gate(s)
Drain
• Contact Areas: 0.4x0.4 um2 to 8x8 um2
• Devices from 50 um to 250 um long
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Process Flow
Elec0 Layer
Pre-alignment
Isolation
Si Substrate
Pattern Elec0
Isolation Growth
6000A Low Temp Oxide
1000A Stoichiometric Silicon Nitride
Main Sacrificial (LTO)
Poly 0 Deposition
Poly 0 Formation
RIE to isolation w/ overetch
Main Sacrificial Deposition
5500A Low Temp Oxide
Dimple hole
Dimple Formation
DRIE to Isolation or timed DRIE
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Process Flow
Fine refill sacrificial (HTO)
Fine Sacrificial Deposition
650A High Temp Oxide
Anchor holes
Anchor Formation
DRIE to isolation layer
Elec1 Layer
Poly 1 Deposition
5500A @ 615C n-doped
Poly 1 Formation
RIE etch to Main Sac
Sacrificial Release
Sacrificial Release
HF:HCl 20’ then critical pt. dry
Process Finished
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