Transcript CSCE 612: VLSI System Design

CSCE 613: Fundamentals of VLSI Chip Design
Instructor: Jason D. Bakos
Topics for this Lecture
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Semiconductor theory in a nutshell
MOSFET devices as switches
Transistor-level logic
Logic gates
IC fabrication
SCMOS design rules
Cell libraries
Fund. of VLSI Chip Design 2
Elements
Fund. of VLSI Chip Design 3
Semiconductors
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Silicon is a group IV element (4 valence electrons, shells: 2, 8, 18, …)
– Forms covalent bonds with four neighbor atoms (3D cubic crystal lattice)
– Si is a poor conductor, but conduction characteristics may be altered
– Add impurities/dopants (replaces silicon atom in lattice):
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Makes a better conductor
Group V element (phosphorus/arsenic) => 5 valence electrons
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Leaves an electron free => n-type semiconductor (electrons, negative carriers)
Group III element (boron) => 3 valence electrons
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Borrows an electron from neighbor => p-type semiconductor (holes, positive carriers)
+P-N junction
+ + ++ + +
--- ---
+ + ++ + +
--- ---
+forward bias
reverse bias
Fund. of VLSI Chip Design 4
MOSFETs
• Diodes not very useful for building logic
• Metal-oxide-semiconductor structures built onto substrate
– Diffusion: Inject dopants into substrate
– Oxidation: Form layer of SiO2 (glass)
– Deposition and etching: Add aluminum/copper wires
negative
voltage (rel.
to body)
(GND)
positive voltage
(Vdd)
NMOS/NFET
current
body/bulk
GROUND
+++
channel
shorter length,
faster transistor
(dist. for
electrons)
PMOS/PFET
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+++
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current
body/bulk
(S/D to body is
reverse-biased)
HIGH
Fund. of VLSI Chip Design 5
FETs as Switches
• NFETs and PFETs can act as switches
CMOS
logic
bulk
node not
shown
“and structure”
“or structure”
pull-up
OFF
pull-up
ON
pull-down
OFF
Z
(floating)
1
pull-down
ON
0
smokin’!
CMOS: assuming PU and
PN network are perfect
switches and switch
simultanously, no current flow
and no power consumption!
Fund. of VLSI Chip Design 6
Logic Gates
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CMOS: complimentary in form and function
NMOS devices (positive logic) form pull-down
network
PMOS devices (negative logic) form pull-up
network
Implication: CMOS transistor-level logic gates
implement functions where may the inputs are
inverted (inverting gates)
Add inverter at inputs/outputs to create noninverting gate
NAND2
Y  A B
Y  A B
inv
YA
NOR2
NAND3
Y  A B
Y  A B
DeMorgan’s Law
A B  A B
Fund. of VLSI Chip Design 7
Compound Gates
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Combine parallel and series structures to form
compound gates

 
Y  A B C  D
Example:
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Use DeMorgan’s law to determine complement (pulldown network):
Y   A  B   C   D
C
A
  
Y  A  B  C  D
Y   A  B   C  D
Y  A B C  D
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B
D
Y
A
C
B
D
Fund. of VLSI Chip Design 8
Pass Transistors/Transmission Gates
• NMOS passes strong 0 (pull-down)
• PMOS passes strong 1 (pull-up)
Pass transistor:
Transmission gate:
Fund. of VLSI Chip Design 9
Tristates
Fund. of VLSI Chip Design 10
Multiplexer
Transmission gate multiplexer
Inverting multiplexer
Fund. of VLSI Chip Design 11
Multiplexer
4-input multiplexer
Fund. of VLSI Chip Design 12
Latches
Positive level-sensitive latch
Fund. of VLSI Chip Design 13
Latches
Positive edge-sensitive latch
Fund. of VLSI Chip Design 14
IC Fabrication
• Inverter cross-section
field oxide
Fund. of VLSI Chip Design 15
IC Fabrication
• Inverter cross-section with well and substrate contacts
(ohmic contact)
Fund. of VLSI Chip Design 16
IC Fabrication
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Chips are fabricated using set of masks
– Photolithography
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Inverter uses 6 layers:
– n-well, poly, n+ diffusion, p+ diffusion,
contact, metal
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Basic steps
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oxidize
apply photoresist
remove photoresist with mask
HF acid eats oxide but not photoresist
pirana acid eats photoresist
– ion implantation (diffusion, wells)
– vapor deposition (poly)
– plasma etching (metal)
Fund. of VLSI Chip Design 17
IC Fabrication
Furnace used to oxidize (900-1200 C)
Mask exposes photoresist to light,
allowing removal
HF acid etch
piranha acid etch
diffusion (gas) or ion implantation
(electric field)
HF acid etch
Fund. of VLSI Chip Design 18
IC Fabrication
Heavy doped poly is grown with gas in
furnace (chemical vapor deposition)
Masked used to pattern poly
Poly is not affected by ion implantation
Fund. of VLSI Chip Design 19
IC Fabrication
Metal is sputtered
(with vapor) and
plasma etched from
mask
Fund. of VLSI Chip Design 20
Layout Design Rules
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Design rules define ranges for features
– Examples:
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min. wire widths to avoid breaks
min. spacings to avoid shorts
minimum overlaps to ensure complete overlaps
– Measured in microns
– Required for resolution/tolerances of masks
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Fabrication processes defined by minimum channel width
– Also minimum width of poly traces
– Defines “how fast” a fabrication process is
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Lambda-based (scalable CMOS) design rules define scalable rules based
on l (which is half of the minimum channel length)
– classes of MOSIS SCMOS rules: SUBMICRON, DEEP SUBMICRON
Fund. of VLSI Chip Design 21
Layout Design Rules
Fund. of VLSI Chip Design 22
Layout Design Rules
• Transistor dimensions are in W/L ratio
– NFETs are usually twice the width
– PFETs are usually twice the width of NFETs
• Holes move more slowly than electrons (must be wider to deliver same
current)
Fund. of VLSI Chip Design 23
Layout
3-input NAND
Fund. of VLSI Chip Design 24
Design Flow
• Design flow is a sequence of steps for design and
verification
• In this course:
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Describe behaviors with VHDL/Verilog code
Simulate behavioral designs
Synthesize behaviors into cell-level netlists
Simulate netlists with cell-delay models
Place-and-route netlists into a physical design
Simulate netlists with cell-delay models and wire-delay models
• Need to define a cell library:
– Function
– Electrical characteristics of each cell
– Layout
Fund. of VLSI Chip Design 25
Cell Library (Snap Together)
Layout
Fund. of VLSI Chip Design 26