Transcript SPI - Personal Web Pages

Serial Peripheral Interface [SPI]
Controller Area Network [CAN]
By:
Instructor:
Praneeth Kumar Bajjuri
Dr.James M. Conrad
SPI
•
•
•
•
•
Overview
Principle of operation
Configuration
Registers
SPI initialization
Overview
• This name was coined by Motorola.
• The Serial Peripheral Interface Bus or SPI bus is a very loose
standard for controlling almost any digital electronics that
accepts a clocked serial stream of bits.
• The SPI is a synchronous serial interface in which data in an 8bit byte can be shifted in and/or out one bit at a time.
• It is a synchronous serial data link that operates in full duplex
• SPI really gains efficiency in applications that take advantage of
its duplex capability.
• SPI can also achieve significantly higher data rates than I2C .
Overview
• During Data transfer the master always sends a byte of
data to slave and slave always sends a byte of data to
master
• Less overhead in SPI than I2C due to lack of
addressing .
• SPI requires more effort and more hardware resources
than I2C when more than one slave is involved [due to
lack of addressing]
• Hence for point to point this is simple and efficient
whereas for multiple slaves more hardware is required.
SPI signals
•
1.
2.
•
1.
2.
Data Signals
MOSI
MISO
Control Signals
SCLK
SS [slave sel]
Operation
• In Master, the bits are sent out of the MOSI pin and received in
the MISO pin.
• The bits to be shifted out are stored in the SPI data register,
SP0DR, and are sent out most significant bit (bit 7) first.
• When bit 7 of the master is shifted out through MOSI pin, a bit
from bit 7 of the slave is being shifted into bit 0 of the master
via the MISO pin.
• After 8 clock pulses or shifts, this bit will eventually end up in bit
7 of the master.
• The frequency of this clock can be controlled by the SPI baud
rate register, SP0BR.
• The SS pin must be low to select a slave.
• Data transfer is always initiated by the master.
Data Transfer Formats
• 2 Parameters, Clock
Polarity (CPOL) and
Clock Phase (CPHA),
determine the active
edge of the clock.
• Master and slave must
agree on parameter pair
values in order to
communicate
CPOL,CPHA
First Data
Driven
Other Data
Driven
Data Sampled
00
Prior to first
SCK Rising
Edge
SCK Falling
Edge
SCK Rising
Edge
01
First SCK
Rising Edge
SCK Rising
Edge
SCK Falling
Edge
10
Prior to first
SCK Rising
Edge
SCK Rising
Edge
SCK Falling
Edge
11
First SCK
Rising Edge
SCK Falling
Edge
SCK Rising
Edge
Configuration
•
•
SPI interface defines only the communication lines and the clock edge
SPI does not have an acknowledgement mechanism to confirm receipt of
data.
• In fact, without a communication
protocol, the SPI master has no
knowledge of whether a slave even exists.
• Flow of Data is not controlled .If needed
External Flow control circuitry is
designed outside SPI.
• Hardware Realization is just by using
simple shift register.
• Supported by all AVR 8-bit μC except ATTiny and some AT90s
• ATmega323
1. PB6=MISO, PB5=MOSI, PB7=SCK, PB4=/SS
2. SPCR – sets bit rate, CPOL, CPHA, M/S
3. SPDR – used for data transfer to and from SPI shift register
Master operation
•
•
•
•
Set the SPI clock counter register to desired baud rate.
Set the SPI control register for desired settings.
Data to be transferred is written in SPI Data register
Wait for status flag to be 1. This flag is set after all the
data is transferred from SPI Data register.
• Always check the status flag.
• Read the Received data from SPI data register [opt].
• Constantly look for data availability to be transferred.
Slave Operation
• Set the SPI control Registers to the desired settings.
• Write data to be transmitted in SPI Data Register.
Possible when the transfer is not in progress. [opt]
• Wait for Status flag bit to be set to 1. this will be set
after the last sampling clock edge of SPI Data transfer.
• Poll the SPI status register.
• Read the received data from SPI Data Register [opt].
• Constantly look for data availability from master.
Registers
Bit
Control Register
[SPCR]
Status
Register
[SPSR]
Data Register
[SPDR]
Clock counter
Register
[SPCCR]
Interrupt
Register
[SPINT]
[2:0]
Reserved
Reserved
CPHA
ABRT
SPI Clock
Counter
Settings
0- SPI
Interrupt
3
SPI Bi
directional
Data port
4
CPOL
MODF
5
MSTR
ROVR
6
LSBF
WCOL
7
SPIE
SPIF
[1:7]-Reserved
SPI Initialization
• Void recv_spi(char *ptr, long
• Void config_spi()
count)
{
{
PINSEL0 = 0x00005500; int i ;
for(i=0;i<255;i++)
IODIR=0x0000000B;
{
SPCR |= 0x20;
SPDR = 0x00;
while(!(SPSR & 0x80));
SPCCR |= 0x08;
ptr[i] = SPDR;
SPDR = 0x44;
count++;
SPINT = 0x00;
}
}
}
Manufacturers OF SPI
Manufacturer
Device Types
AKM
EEPROM
Analog Devices
DSP, ADC, digital Poti
Atmel
EEPROM, digital Poti
Crystal
ADC
Dallas
RTC
EPSON
RTC
Fairchild
EEPROM
Infineon
Pressure Sensor
Intel
CAN Controller
Linear Technology
ADC, DAC, Temperature Sensor + Voltage Monitor
Macronix
FLASH
Maxim
ADC, DAC, UART, Analog Switches
Microchip
Micro controller, EEPROM, ADC, CAN controller
Motorola
DSP, MCU
National Semiconductor
LCD Controller, dig. Temperature Sensor, USB Controller
NeXFlash
FLASH
RAMTRON
FRAM
SanDisk
FLASH, MultiMediaCard
SGS-Thomson
EEPROM, Micro controller
Texas Instruments
DSP, ADC, DAC
Xicor
CPU Supervisor, EEPROMs, FLASH
Zilog
DSP
CAN Protocol
•
•
•
•
•
•
•
•
History
Definition
Standards
Operation
Message Format
Data Link Layer
Physical Layer
Applications
History
• CAN was first developed by Robert Bosch GmbH, Germany in 1986 when
they were requested to develop a communication system between three ECUs
(electronic control units) in vehicles by Mercedes.
• They found that an UART is no longer suitable in this situation because it is
used in point-to-point communication. The need for a multi-master
communication system became imperative.
• Is a high-integrity serial data communications bus for real-time applications
• Operates at data rates of up to 1 Megabits per second
• Has excellent error detection and confinement capabilities
• It is now being used in many other industrial automation and control
applications
• International standard: ISO 11898
• sophisticated error detecting mechanisms and re-transmission of faulty
messages. This also guarantees data integrity.
Definition
• CAN is a serial bus system with multi-master capabilities, that is, all CAN
nodes are able to transmit data and several CAN nodes can request the bus
simultaneously
• A sender of information transmits to all devices on the bus. All receiving
devices read the message and then decide if it is relevant to them. This
guarantees data integrity as all devices in the system use the same information.
• Multi-Master Hierarchy: If one network node is defect the network is still able
to operate.
• It is a two-wire, half duplex, high-speed network system and is well suited for
high speed applications using short messages.
• CAN can theoretically link up to 2032 devices (one node with one identifier)
on a single network.
• However, due to the practical limitation of the hardware (transceivers), it can
only link up to110 nodes (with 82C250, Philips) on a single network.
Principle of operation
•
•
•
•
•
•
•
•
It uses Carrier Sense multiple Access with collision Detection along with Arbitration
on message priority [CSMA/CD +AMP].
Data messages transmitted from any node on a CAN bus do not contain addresses of
either the transmitting node, or of any intended receiving node.
Instead, the content of the message is labeled by an identifier that is unique
throughout the network .
This identifier is the principle part of the CAN arbitration field, which is located in the
beginning of each CAN message.
All other nodes on the network receive the message and each performs an acceptance
test on the identifier to determine if the message, and thus its content, is relevant to
that particular node.
If the message is relevant, it will be processed; otherwise it is ignored.
The unique identifier also determines the priority of the message.
The higher priority message is guaranteed to gain bus access as if it were the only
message being transmitted. Lower priority messages are automatically re-transmitted in
the next bus cycle
Principle of operation
• The bits in a CAN message can be sent as either high or low.
• The low bits are always dominant, which means that if one node tries to send
a low and another node tries to send a high, the result on the buse will be a
low.
• A node that sends a high in the arbitration field and detects a low knows that
it has lost arbitration. It stops transmitting, letting the other node, with a
higher priority message, continue uninterrupted.
• Two nodes on the network are not allowed to send messages with the same
id.
• If two nodes try to send a message with the same id at the same time
arbitration will not work. Instead, one of the transmitting nodes will detect
that his message is distorted outside of the arbitration field. Error Handling
Scheme will take care of this.
Frames in CAN
• Data frames are used when a node wants to transmit
data on the network, and are the "normal" frame type.
• Remote frames can be described as a request for
information. A frame with the RTR bit set means the
transmitting node is asking for information of the type
given by the identifier .
• Simpler CAN controllers (BasicCAN) can not respond
automatically. In this case the host microcontroller is
made aware of the remote request and has to send the
data.
Message Format
• Standard CAN 2.0A format
• Extended CAN 2.0B format
Message Formats
•
•
1.
2.
•
•
2.0B controllers are completely backward compatible with
2.0A controllers and can transmit and receive messages in
either format.
There are 2 types of 2.0A controllers
The first is capable of transmitting and receiving only
messages in 2.0A format. With this type of controller,
reception of any 2.0B message will flag an error.
The second type of 2.0A controller (known as 2.0B passive) is
also capable of sending and receiving 2.0A messages, but in
addition, these devices will acknowledge receipt of 2.0B
messages and then ignore them.
The number of unique identifiers available to users, on a single
2.0A network, is 2,032 (2 to the power 11 - 2 to the power 4).
The number of unique identifiers available on a 2.0B network
is in excess of 500 million!
Data Link Layer [ISO 11898]
1.
2.
3.
4.
Bus Arbitration
Error Detection
Error Signaling
Error Confinement
Error Detection
•
•
•
•
•
•
1.
2.
•
1.
2.
3.
This Process is done automatically by a CAN controller.
The error is detected by the a CAN controller (a transmitter or a receiver).
An error frame is immediately transmitted.
The message is cancelled at all nodes
The status of the CAN controllers are updated. The message is re-transmitted. If several controllers have
messages to send, normal arbitration is used.
Type of Errors:
Bit errors:
Bit stuffing error - normally a transmitting node inserts a high after five consecutive low. This is called bit
stuffing. A receiving node that detects violation
Bit error: A transmitting node always reads back the message as it is sending. If it detects a different bit
value on the bus than it sent, and the bit is not part of the arbitration field or in the acknowledgement field,
and error is detected.
Message errors:
Checksum error - each receiving node checks CAN messages for checksum errors.
Frame error - If a receiver detects an invalid bit in one of these positions of a frame a Form Error will be
flagged.
Acknowledgement Error - If a transmitter determines that a message has not been Acknowledged then an
ACK Error is flagged.
Error Modes
•
•
•
Error active - the normal operating mode for a controller.
Messages can be received and transmitted. On detecting an
error an active error flag is sent (see error signaling).
Error passive - a mode entered when the controller has
frequent problems transmitting or receiving messages.
Messages can be received and transmitted. On detecting an
error while receiving, a passive error flag is sent.
Bus off - entered if the controller has serious problems with
transmitting messages. No messages can be received or
transmitted until the CAN controller is reset by the host
microcontroller or processor.
Bit Timings
•
Each bit is divided into four segments
1.
Synchronisation segment (Synch_Seg): The synchronisation segment is
used to synchronise the various nodes on the bus. When a bit is sent on the
bus, the leading edge is expected to be within this segment.
Propagation segment (Prop_Seg):The Propagation Segment is needed
to compensate for the delay in the bus lines.
Phase Segment 1 (Phase_Seg1), Phase Segment 2 (Phase_Seg2):
These segments can be used lengthened or shortened by
resynchronization.
2.
3.
Physical Layer
• CAN transmits signals on the CAN bus which
consists of two wires, a CAN-High and CAN-Low.
• These 2 wires are operating in differential mode, that
is they are carrying inverted voltages (to decrease noise
interference)
• CAN High Speed
[ISO 11898]
• CAN Low Speed
[ISO 11519]
CAN Implementation
Basic CAN
Full CAN
Transmit
It fills complete TX register
including ID, RTR, data length ,
data
Transmit mailboxes initialized
once
Only data bytes written before
transmission
Receive
Every CAN message can be
received
Only IDs defined in the receive
mailboxes can be received
Remote Frame Handling
Frames are answered by the
application
Frames are answered
automatically by the controller
Overrun Philosophy
Keep the oldest message [new
message will be lost]
Keep the newest message [old
message will be lost]
References
• SPI
1. [http]: http://www.embedded.com/showArticle.jhtml?articleID=9900483
2. [http]: http://www.rpi.edu/dept/ecse/mpsd/SPI.pdf
3. [http]: http://www.answers.com/topic/serial-peripheral-interface-bus
4. [http]: http://www.mct.net/faq/spi.html
5. [http]: http://www.maxim-ic.com/appnotes.cfm?appnote_number=802
6. [http]: http://controls.ame.nd.edu/~bill/microcontroller/main/node28.html
7. [http]: http://www.ece.osu.edu/ie/main/CurrentResearch/SPI_Nautilus_chip/
__________________________________________________________________________
•
1.
2.
3.
CAN
[http]: http://www.can-cia.org/can/
[http]: http://www.algonet.se/~staffann/developer/CAN.htm
[http]:
http://zone.ni.com/devzone/conceptd.nsf/webmain/264668060CFB196286257067007E57D4
Thank you
• Any Questions?
?