Transcript (35mW) to 1kS/s (15 µW)

A 50MS/s (35mW) to 1kS/s (15μW) Power
Scaleable 10b Pipelined ADC with Minimal Bias
Current Variation
Potential applications:
 Flexible systems
 reconfigurable bandwidth
 multi-standard
 multi-rate processing
 Industrial applications
 Single ADC targeted for
different applications
Previous approaches
 Bias current scaling
 Can shift transistors
into weak inversion
 Suffer from poor yield
 Multiple operating
corners to verify
University of Toronto
This work
ADC power
tON
tOFF
• Power off ADC between output
conversions
• Challenge for high speeds:
need rapid power-on of analog
• Developed rapid power-on
opamp
1
tON
Ts1
fs2<fs1
P2-avg<P1-avg
tOFF
2
Ts2
time
tON
Pavg = PON
= PON
tON + tOFF
tON
Ts
= PONtONfs
PD
VB1
VB3
PD
+
An
PD
vout-
Ap+
-
PD
PD
PD
vin-
vin+
PD
PD
PD
-A
n
+
+Ap
PD
Rout ≈ Apgm2ro2ro1
PD
vout+
VB1
C1
PD
+
Ap
Cp
VB3
M2
PD
VB2
Cp<<C1
M1
Summary
• Architecture multiplies
power scalable range of
current scaling by 50x
Technology
1.8V, 0.18μm CMOS
Resolution
10 bit
Full scale input
1.6V p-p
1.2mm2
Area
fs (power) range
1kS/s (15μW) - 50MS/s (35mW)
bias current scaling
1:50
Performance at 50MS/s
Power
35mW
SNDR (fin=20.94MHz)
55dB (8.8b ENOB)
SFDR (fin=20.94MHz)
67dB
DNL/INL
0.63/-0.91, 1.06/-1.2
• Novel rapid power-on
opamp to enable power
scaling at high sampling
rates
1000
power (mW)
100
[JSSC, 00]
[JSSC, 03]
10
[ESSCIRC, 04]
[JSSC, 04]
[ISSCC, 05]
1
[ISCAS, 00]
ADI7811
0.1
0.01
MAX1087
[TCAS-I, 04]
0.001
1.E+03
1.E+04
this work
1.E+05
1.E+06
1.E+07
sampling rate (S/s)
published results
industry data sheets
1.E+08