Transcript Dynamically Parameterized Architectures for Power Aware Video

Adaptive System on a Chip (ASOC):
A Backbone for Power-Aware
Signal Processing Cores
Andrew Laffely, Jian Liang, Russ Tessier and Wayne Burleson
Electrical and Computer Engineering
University of Massachusetts Amherst
{burleson}@ecs.umass.edu
This material is based upon work supported by the National Science Foundation under Grant No. 9988238
and SRC Tasks 766 and 1075
Burleson, UMASS
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Challenges in Media Processing
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Increasingly complex, heterogeneous algorithms
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Large data-sets, usually streaming
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Variable run-times (e.g. data-dependent iterations)
Variable quality
Variable power consumption
Memory size, ports and latency issues
Advancing semiconductor technology (Moore’s Law)
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Interconnect (on-chip and I/O)
Clocking
Power (consumption and distribution)
Design and Verification
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aSoC: adaptive System on a Chip
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Motion Estimation
and Compensation
DCT
Control Encrypt
VLE
FIR
Tiled SoC
architecture
Viterbi Memory
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aSoC: adaptive System on a Chip
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Motion Estimation
and Compensation
DCT
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Tiled SoC architecture
Supports the use of
independently developed
heterogeneous cores
Pick and place cores which
best perform the given
application
• Increase performance
• Save power
• Cores may be any number
of tiles in size
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Control Encrypt
FIR
VLE
Viterbi Memory
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aSoC: adaptive System on a Chip
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Motion Estimation
and Compensation
DCT
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Control Encrypt
FIR
VLE
Tiled SoC architecture
Supports the use of
independently developed
heterogeneous cores
Connected with an
interconnect mesh
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Restricted to near neighbor
communications
• Creates pipeline
• Decreases cycle time
Viterbi Memory
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aSoC: adaptive System on a Chip
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Motion Estimation
and Compensation
DCT
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Control Encrypt
VLE
Tiled SoC architecture
Supports the use of
independently developed
heterogeneous cores
Connected with an optimized
fixed interconnect mesh
Using a communication interface
(CI) to manage data
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FIR
Viterbi Memory
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Network port (Coreport) for each
core, I/O queues,handshake
Each CI uses a memory and FSM
to repetitively process a
predefined (static) schedule of
communications
High-speed 5x5 bidirectional
crossbar
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Communication Interface
Core
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Core-ports
North
North
South
East
South
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East
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West
West
Inputs
Local Config.
Crossbar
Decoder
North to South & East
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Outputs
Controller
Custom design to
maximize speed
and reduce power
Local
Frequency
& Voltage
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Core-ports
Crossbar
Controller
Instruction
memory
Local frequency
and voltage supply
PC
Instruction Memory
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aSoC Implementation and Integration
2500 l
.18m TSMC technology
Full custom
3000 l
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Research Thrusts
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aSoC Infrastructure1,3
• Communication Interface
• Interconnect3
• Power Distribution
• Clock System
• Power Management
Design Technology
• Compiler1,3 (Partitioner,
Mapper, Placer, Scheduler)
• Simulator1
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Cores
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Motion estimation2,3
Discrete Cosine Transform2,3
AES Cryptography3
Huffman Coding
Adaptive Viterbi2,3
3D Graphics1,2,3
Smart Card2,3
MP3
ARM
DSP
• Cache2,3
• FPGA
• MAC
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2
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PhD Dissertation
Masters Thesis
Publications
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Voltage Scaling Approach
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Core-ports
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Single buffer for each
stream to cross
clock/voltage barrier
between core and
interface
Reading/Writing
success rates indicate
core utilization
Input blocked: Core
too slow
• Output blocked:
Core too fast
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Controller
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Interprets core-port
success rates to adjust
local clock and voltage
Core
Buffer
Processing
Pipeline
Local Local
Vdd Clock
Input
Core-port
Output
Core-port
Clock
Blocked
Blocked
and
Supply
Controller
Interconnect
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Vdd Selection Criteria
Normalized Core Critical Path Delay vs. Vdd
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Normalized
Delay 10
1/8 Speed 8
6
1/4 Speed 4
1/2 Speed
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As Vdd decreases delay increases
exponentially
Use curve to match available clock
frequencies to voltages
The voltage and frequency change
reduces power by 79%, 96%, and
98.7%
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P = aC(Vdd)2f
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Max Speed
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0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
0.73 1.16
2
Voltage
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Architecture Evaluation
(Motion Estimation)
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Array-based
architecture
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Memory
Pipelined ME
FIFOs
Parameterized
search window
size
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Address
Generation
Unit
Full search
Choose 16x16 or
8x8 windows
Reduce power
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Processing
Element
Array
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Power Aware Core
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Custom motion estimation core
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Choose search method
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Full search
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Spiral search
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960-600mW (bit width and pel sub-sampling)
76mW
Three step search
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25mW
Data taken with SynopsysTM Power Compiler at the RTL level
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aSoC Support
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Coreports
in1
Stream A
Motion
Estimation
Core
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Easy to manage on both
sides of the port
Schedule configuration
streams in with the data
Stream A: Input Frame
• Stream B: Configuration
(Choose search mode and
size)
• Stream C: Motion Vectors
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in2 out1 out2
Stream B
Multiple streams in and out
through dedicated core ports
Stream C
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Reconfigurable Interconnect
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P-frame
+
Input
Frame
DCT
ME
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S
MC
I-frame
Input
Frame
DCT
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aSoC Support
Motion Estimation
& Compensation
DCT
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Lumped ME, MC and
Summation into one
double core
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aSoC Support: P-Frame
Motion Estimation
& Compensation
Input
Frame
(Stream A)
DCT
Difference
Frame
(Stream B)
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aSoC Support: Schedule Change
Input
Frame
(Stream A)
Motion Estimation
& Compensation
DCT
Difference
Frame
(Stream B)
Configuration Streams (C & D)
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aSoC Support: Schedule Change
Input
Frame
(Stream A)
PC
Motion Estimation
& Compensation
Schedule 1
DCT
Difference
Frame
(Stream B)
Schedule 2
Configuration
(Streams C)
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aSoC Support: Schedule Change
Input
Frame
(Stream A)
PC
Motion Estimation
& Compensation
Schedule 1
DCT
Difference
Frame
(Stream B)
Schedule 2
Configuration
(Streams C)
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aSoC Support: Schedule Change
Input
Frame
(Stream A)
Motion Estimation
& Compensation
PC
DCT
Schedule 1
Schedule 2
Configuration
(Streams D)
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aSoC Support: Schedule Change
Input
Frame
(Stream A’)
Motion Estimation
& Compensation
PC
DCT
Schedule 1
Schedule 2
Configuration
(Streams D)
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aSoC Support: I-Frame
OFF
Input
Frame
(Stream A’)
Motion Estimation
& Compensation
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DCT
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Operating Frequency?
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Interconnect synchronized
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Core frequencies depend on critical path
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H-tree clock distribution
Tile provides clock reference
Coreport provides asynchronous boundary
Dynamic core configuration requires dynamic
clock configuration
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aSoC clock reference provides multiples of
interconnect clock (… 4x, 2x, 1x, 0.5x, 0.25x, …)
Configured through the tile controller
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Clock Distribution
Tile
• Tiled architecture extends life
of globally synchronous
systems
• Precise H-tree implementation
• Load is small and equal at each
branch
• Skew can be reduced by 70%
with advanced deskew circuits1
64 tile aSoC
70nm
100nm
130nm
180nm
Chip Area
(9.24mm)2
(13.3mm)2
(17.2mm)2
(23.8mm)2
Frequency
5 GHz
2 GHz
1 GHz
0.5 GHz
Power
126 mW
240 mW
445 mW
784 mW
Mean Skew
41 ps
50 ps
92 ps
70.6 ps
Percent Skew
21 %
10 %
9%
4%
S. Tan et al. “Clock Generation and Distribution for the First IA-64 Microprocessor”
IEEE JSSC, Nov. 2000
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Mixed vs. Fixed Core Frequencies
Core: Mode
ME:
Full Search
ME:
Spiral
ME:
Three Step
Search
DCT
Interconnect
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Optimal Independent
Frequencies
Frequency
Power
MHz
mW
105
973
Fixed Worst Case
105MHz
Power
mW
973
9.9
76
659
2.75
25
580
9.6
6.34
54
0.14
349
0.81
Cores not designed with clock gating
Core power from Synopsys RTL simulation
Interconnect from SPICE
Assumes 10 cycle schedule, 4 pixels/word
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Current Density and Clocking
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ME: Full
Search
Red: fixed worst case clocking
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ME:
Spiral
Green: optimal independent
clocking
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ME: Three
Step Search
Current
Short spikes of high current
Slow and low
Optimal clocking eliminates
current spikes (also improved
battery life)
DCT
Time
Process Start
Deadline
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Power Distribution
• Heterogeneous power-aware
cores require multiple power
supply voltages
• Tile structure enables
uniform interwoven grid
• Larger grid for higher current
demands
Gnd
Vml
Vl
Vmh
• Reduced resistance
• Higher capacitance
Vh
64 tile aSoC
Vh
Vmh
Vml
Vl
Voltage
1.8V
1.16V
0.73V
0.6V
Current
per Core
110mA
25mA
13mA
7mA
Total Power
12.1 W
1.86 W
607 mW
269 mW
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Advanced Signaling Techniques
(building on SRC-funded work)
Differential current sensing
Booster Insertion
Multi-level current signaling
Phase coding
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Interconnect Characterization:
Comparing delay and power of signaling techniques for different
tile sizes at 250nm, 180nm, 130nm, 100n (available via web-based
tool Network on Chip Interconnect Calculator NOCIC)
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Conclusions
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Regular Tiled Architecture
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Static scheduling
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High-level global schedule of inter-core communication
Accomodates dynamic workloads with queues and local handshakes
Demonstration using Motion Estimation and DCT
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Task-based parallelism using heterogeneous cores
Predictable interconnect
Regular core interface, Vdd and clock control, and configuration control
Variable search window and search algorithm provide power/quality tradeoff
Power savings using scalable approaches to dynamic clock and power
variation
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Simple clock dividers leveraging existing clock distribution methods
Route multiple power supplies to allow rapid switching and avoid overhead of
on-chip power regulation
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Ongoing Work
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Satellite Set-top Box application
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New and more complete wireless and multimedia systems
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Jpeg2000, mpeg-4, 3d Graphics, …
ASOC parameter optimization
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Developed at Hughes Networks using 7 distinct RISC cores. Compare ASOC with
in-house shared memory approach for interconnections.
Tile sizes, bus widths, clocks, VDDs
Coping with Core irregularity
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Size, I/O positions, shapes, bus widths, communication interfaces
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Interconnect circuit optimization (NoCIC)
Leakage Power issues
Reliability, Test, Fault-Tolerance and Security
Compilation: especially Partitioning, Mapping
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Prototypes: .18u MOSIS of communication interface, ~25K transistors,
verification of interface logic and timing
ASOC in Education: Circuits, architecture and core design projects
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Implications (perhaps controversial )
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Multi-core architectures will be needed to maintain
Moore’s law (interconnect, memory, parallelism)
Task-based parallelism may be easier to program,
extract and implement than data parallelism (think
multi-core rather than instruction level parallelism)
Global coarse synchronization provides an approach to
hard-real time computing for dynamic workloads (ie
video coding).
Dynamic Power savings exploiting fine-grain workload
variations can be achieved through straightforward
clock and power scaling methods.
Interconnect standards will be specified by silicon
foundries similar to cell libraries and memories
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Design Flow
http://vsp2.ecs.umass.edu/vspg/658/TA_Tools/design_flow.html
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Architecture to Layout
Architecture: Block diagram of system and behavioral description
Logic: Gate level or schematic description
• Circuit: Transistor configurations and sizings
• Layout: Floorplanning, clock and power distribution
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Tools
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VerilogXL: behavioral representation
VTVT: standard cell library
Synopsys: standard cell gate level netlist generation
Silicon Ensemble: standard cell netlist to layout
Cadence LayoutPlus: schematic and layout design
NCSU CDK: design and extraction rules
Cadence Layout vs. Schematic: layout verification
HSPICE: circuit simulator
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