Transcript Channel Control ASIC for the CMS Hadron Calorimetry Front End

Channel Control ASIC for the
CMS Hadron Calorimeter Front
End Readout Module
Ray Yarema, Alan Baumbaugh, Ahmed
Boubekeur, John Elias, Theresa Shaw
September 12, 2002
September 8-14, 2002
7th Workshop on Electronics for LHC
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CCA Use in CMS
• CCAs are used for processing both HPD and PMT
signals
• CCA provides control and interface for QIE
ASICs which digitize charge input signals.
• CCAs and QIEs are mounted on the CMS Hadron
Calorimeter Front End Readout Module
• CCAs and QIEs were designed at Fermilab
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Front End Readout Module
• Two QIE chips
interface to one
CCA chip
• There are 3
CCA chips on a
Front End
Readout Module
• 3 CCAs feed
data to 2 GOLs
From
HPD or
PMT
Front End Readout Module
QIE
CCA
QIE
GOL
VCSEL
GOL
VCSEL
QIE
CCA
QIE
QIE
CCA
QIE
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Hadron Calorimeter Front End Module
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What is a QIE?
(Charge Integrator and Encoder)
• QIE digitizes input signal over
a wide dynamic range
• QIE operates in a 4 step
QIE Clock
pipeline mode
• The data is output as a 2 bit
HPD Input
exponent and 5 bit mantissa
along with the time slice
information which is referred to
PMT Input
as Cap ID
• QIE can be programmed to
accept either positive (PMT) or
negative (HPD) input charge
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QIE
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Exponent
5
Mantissa
2
Cap ID
5
Primary Functions of CCA
• Send individually programmable delayed
clocks to each of the QIEs, to correct for
time differences within the hadron
calorimeter (58 nsec max)
• Accept exponent and mantissa information
from 2 QIEs, align the data and send the
data to a gigabit serializer that drives an
optical link
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Other CCA Features
• Provide RBX serial
interface, similar to I2C,
for programming features
• See that QIEs are
operating in sync by
checking QIE capacitor
IDs
• Force QIE into fixed range
instead of autoranging for
test purposes
• Adjust QIE pedestal level
to correct for HPD leakage
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• Reset QIEs
• Place QIE in calibration
mode
• Issue test pulse triggers of
programmable polarity for
either HPD or PMT
• Flag zero crossing counter
check error
• Test pattern registers to
check operation of DAQ
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CCA Connections
• Figure on the
right shows
connections for
1 QIE feeding ½
of a CCA
followed by the
GOL
• Chip address
lines RBX_A are
programmed by
6 hard wire
connections on
circuit board
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One set
CCA
Control
Signals
RBX_DATA
RBX_CLK
RBX_A
LHC Clock
BC_Zero
DATA
CNTRL
TX_DATA 18
SEND_FF
6
TEST PULSEa
QIE
From with
Integrated
HPD
or PMT FADC
QIE EXPa
QIE MANTa
QIE CAPIDa
2
5
2
QIE CLKa
2
QIE RESETa
PED_DACa
4
EN_QIE_RANGE
QIE_RANGE 2
CALIB_MODE
1/2
CCA
Repeated
for 2nd QIE
To second QIE
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Operation of CCA Blocks
• RBX interface and registers
• Delay Lock Loop for QIE clock adjustment
• QIE data alignment and data formatting for
GOL
• Other miscellaneous circuits
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RBX Interface and Registers
• CCA chip address is set by 6
hard wire connections on PCB
• RBX bus is a 2 wire
communication interface which
is similar to I2C
• All data is down loaded, 8 bits
at a time, through RBX_DATA
line with each RBX bus cycle
• RBX clock is intended to run at
100Kbits/sec
• RBX data is transferred either
to or from the 1)Pointer
Register or the 2) Data Register
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• The Pointer Register points to 1
of 28 eight bit internal registers.
• Data Register contains data to
be written or read from pointer
address location
• The Pointer Register
automatically increments after
each data transfer to reduce
chip communication overhead
• All registers designed with SEU
tolerant latches to reduce SEU
effects
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Control Register Space and QIE Clock
Adjustment
RBX CLK
Control Register Space
RBX Bus Interface
RBX_Pointer Address
RBX_DATA Data
RBX_DATA
6
RBX_A
4
CALIB_MODE
Control Register
(8 different
controls)
EN_QIE RANGE
QIE_RANGE
2
Alignment
Registers
CCA address
is set by 6
hard wire
connections
on PC board
PED_DACa
PED_DACb
Pedestal DAC
Register
DLL Tap Select
Register QIEa
DLL Tap Select
Register QIEb
5
5
Test Pulse Bunch
Match Register
LHC
clock
Delay
Lock
Loop
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4
QIEa
QIE 2
CLK mux CLKa
QIE 2
QIEb
CLK mux CLKb
Signal to QIEs
Test Pattern
Registers (20)
CCA Internal
controls
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CCA Internal Control Registers
• Control register – 1 register – sets various internal CCA controls and
control settings for QIEs
• Alignment Control registers – 2 registers, 1 for each of 2 QIEs –
selects various timing options to permit channel operation with timing
differences up to 58 ns.
• Pedestal DAC Register – 1 register for 2 QIEs – 4 bits of adjustment
for each of 2 QIE’s to correct for HPD leakage current changes
• DLL Tap Select 0 Register – 1 register – choose clock delay for QIE0
in 1 ns increments from 0 to 25 ns
• DLL Tap Select 1 Register – 1 register – choose clock delay for QIE1
in 1 ns increments from 0 to 25 ns
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CCA Internal Control Registers
(continued)
• Test Bunch Counter Match Register -1 register - contains the Bunch
Count at which a test pulse should be fired for the 2 QIEs, providing
the “Enable Test Pulse” bit has been set in the Control Register
• Test Pattern Registers – 20 registers – contains data or test patterns
that are sent from the CCA through the GOL for 2 reasons:
– To verify proper DAQ communication
– To load data to a specific chip location and verify that the optical cable has
been connected to the correct channel
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Typical Download to CCA Via RBX Bus
Word #
1
A7:A2 (Chip address) A1=0 (Pointer) A0=0 (Write)
2
A7:A2 (Internal register address loaded into Pointer Register)
3
A7:A2 (Chip address) A1=1 (Data) A0=0 (Write)
4
A7:A0 (Data to be loaded into nth Internal Register)
5
A7:A0 (Data to be loaded into n+1 Internal Register)
6
Pointer
register
increments
automatically
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Delay Locked Loop
• Delay Locked
Loop has 25
one nsec taps
to provide fine
control of QIE
clocks
• Each tap stage
is comprised
of 2 inverters
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QIE
Clock
4
25 to 1 Multiplexer
Delay
select
25
1
Control voltage
Input
clock
Phase
Detector
Charge
Pump
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Filter
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QIE Data Alignment and Transmission
• Bits from Control
Register set 4 muxs
in Data Alignment
block for proper
data alignment
• Cap IDs are
checked for proper
synchronization
• Data Mux sends
either Orbit
message or QIE
data at 40 MHz
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Mux controls
Orbit message
Controls from alignment register
From
QIEa
QIE_EXPa
7
2
Sync_
CapIDa 2
Sync_
CapIDb 2
2
QIE_MANTa 5
QIE_CAPIDa 2
QIE_EXPb
From
QIE_MANTb
QIEb
QIE_CAPIDb
CapID
error
QIE Data
Alignment
18
TX_DATA
18
Data
Mux
QIE
Cap ID
Check
QIE DATA
SEND FF
CNTRL
DATA
18
Signals
to GOL
5
2
LHC_CLOCK
LHC_CLOCK
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Typical Data Transmission
• When Bunch
Crossing Zero is
received, an
Orbit Message is
sent and at the
same time the
QIEs are reset
with Cap ID=0.
• QIE data is sent
after the Orbit
Message
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Word Count
Cap ID error(1) Bunch error(1)
Orbit
Irrelevant(4)
message Crossing number(12)
Fill Frame(18 ones)
QIE Data
Orbit
message
0
1
Fill Frame(18 ones)
Data (18 bits)
69
70
Data (18 bits)
Data (18 bits)
3562
3563
Next Orbit Message
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Other CCA Circuits
• Bunch Counter – 12 bit counter that starts at 0 and increments with
the LHC clock. Before reset at next Bunch Crossing=0, counter value
is compared to expected value in the Event Checker. Any errors are
flagged. The BC value is also stored for transmission in Orbit Message
• Test Pulse Trigger Comparator – Produces a Send_Test_Pulse signal
when number in the Test Pulse Bunch Count Match Register equals the
Bunch Counter number. Pulse is 1 cycle long. Polarity is settable
through a bit in the Control Register.
• Synchronizer – Synchronizes test pulses for the 2 QIE which have
different clock delays so the test pulse occurs in the same time slice.
Also Syncs QIE reset pulses.
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Delay
Lock
Loop
6
RBX
Address
RBX_Pointer
RBX_DATA
RBX Bus Interface
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QIE_MANTa
QIE_CAPIDa 2
2
QIE_EXPa
LHC_CLOCK
QIE_EXPb
2
From
QIEb QIE_MANTb 5
QIE_CAPIDb 2
From
QIEa
4
12
7
QIE DATA
Sync_
CapIDb 2
Sync_
CapIDa 2
Select Orbit
Message source
QIE
Cap ID
Check
CapID
error
Data
Mux
TEST
PULSEb
TEST
PULSEa
QIE
RESETb
QIE
RESETa
Signals
to
QIEs
QIE_CLKb
2
4
4
QIE_CLKa
2
Signals
to GOL
DATA
CNTRL
SEND FF
TX_DATA
18
Mux controls
BC_Zero
Send
test
pulse
7
BC_Zero
LHC_CLOCK
QIEb
CLK mux
QIEa
CLK mux
PED_DACa
PED_DACb
CALIB_MODE
EN_QIE RANGE
QIE_RANGE
2
LHC_CLOCK
18
18
Send Fill Frames
Orbit
Message
Enable
Polarity
5
5
Test Pulse
Trigger
Comparator
Test Pattern
Registers (20)
Test Pulse Bunch
Match Registers
DLL Tap Select
Register QIEb
DLL Tap Select
Register QIEa
Pedestal DAC
Register
Alignment
Registers
Control Register
(8 different
control functions)
Control Register Space
Bunch Count
Sync Error
Data
Address
QIE Data
Alignment
Controls from
alignment register
Event Sync
Check
Bunch Counter
BC_ZERO (12 bits)
LHC
clock
CCA address
is set by 6
hard wire
connections
on PC board
RBX_DATA
RBX CLK
Synchronizer
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CCA chip
• Aligent 0.5 u
CMOS process
• 3.4 x 4.0 mm
die
• 128 QFP, 14 x
20 mm
• Production run
of 11400 parts
(22800
channels)
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Test Data
• 500 parts packaged for testing
• 21 separate tests in test program
• 200 parts measured to set cuts in test
program for power supply current (+/15%) and delay time (+/- 2 ns)
• 227 parts were tested with cuts
• 222 good parts for yield of 97.8%
• Remaining 10, 900 parts to be packaged
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Conclusion
• Production quantity of CCA has been
received for the Hadron Calorimeter
• All performance specifications have been
met
• The CCA has been successfully run on a
Front End Module with the QIEs
• The yield from testing the first 200 parts is
very high.
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Acknowledgements
• The authors want to thank
– Abder Mekkaoui for significant contributions
throughout the development of the CCA
– William Wester and Christian Gingu in the
ASIC test group at Fermilab for the yield
information that was used
– Jim Hoff and Alpana Shenai for layout
assistance
– Al Dyer for his test assembly assistance
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