Transcript Topol_IBM_NGCM2004_II_4

IBM Research – T. J. Watson Research Center
CONTACT SCALING
FOR ADVANCED CMOS
Anna W. Topol
C. Lavoie, C. Cabral, L. Chan, L. Sekeraic, S. Mcnab,
D. Fired, J. Hergenrother, J. Sleight, N. Fuller, G. Gibson,
K.
Wong, S. Rossnagel, K. Kwietniak, J. Ott, G. Cohen, L. Sigal,
T. Dalton, R. Viswantathan, H. Deligianni, K. Guarini, M. Ieong
Research
Outline
 Contact Scaling Background & Motivation
– Improvement Trends for IC devices
– Effect of Scaling Trends on Future CMOS technology
 Silicide Contact Resistance for Scaled CMOS Devices
– Bulk and SOI technology challenges
– Proposed solutions
 Options for Lower Resistance Scaled Metal Contacts to Silicides
– Trends
– Impact on circuit performance
– Proposed integration schemes
 Conclusions and Future Directions
Anna W. Topol, NGCM, September 2004
Research
Motivation for CMOS Feature Scaling
 Improvement Trends for ICs Enabled by Feature Scaling
– Speed (Microprocessor clock rate, GHz)
– Compactness (Small and light-weight products)
– Functions per chip (~500 million transistors ‘2004 to ~ 1000 in 2007)
– Cost per function (Decrease of ~25% per year
=> market growth of micorelectronics averaging ~17% per year)
– Integration level (Increasing number of components per chip)
=> min. 10 metal wiring levels
Scaling Trends for ICs
2004
Microprocessor Speed [GHz]
~4.2
½ Pitch (un-contacted poly) [nm]
90
Printed Gate Length [nm]
53
Physical Gate Length [nm]
37
2005
~5.2
80
45
32
2006
~6.7
70
40
28
Anna W. Topol, NGCM, September 2004
2007
~9.3
65
35
25
Research
Effect of Scaling Trends on Contact Technology
 Lithography
− Post etch and resist slimming
(Reduced critical dimension (CD) control & linewidth tolerance margin)
− High mask cost (immersion technology only up to 45 nm technology node)
 Integration
− Need non-classical device concepts & related novel material options
 Performance
– Increased leakage currents & resistance of various device components
(Due to a physical limitations of current generation of materials)
Anna W. Topol, NGCM, September 2004
Research
Device Resistance Components
Rtot  2 Rsd  2( Rco  Rsp  Rov )
Nsd(x)
Nm,dp
N dp ( y )  N mdpe
N ext ( x )  N m ,ext e  k ext y
2
 k d2p y 2
2
N ov ( x)  N ext e  kovx
2
Nm,ext
Nsub
x
Lcon
Silicide
Ru,co
Rsw,co
Ru,co
Rco
Components:
 Silicide Contact Resistance: Rco
 Overlap Sheet Resistance (Rov)
Spacer
2
Gate
R
Rsw,co Rdp,sp Rext,spRspr,ov ac,ov
Buried Oxide
Rdp,sp Rext,sp Rspr,ov
Rsp
Rac,ov
Rov
 Spreading Resistance (Rsp)
 Small Linkup Resistance (Rlink-up)
Anna W. Topol, NGCM, September 2004
Research
Overall Parasitic Resistance (ITRS 2003)
Scaling Trends for ICs
2004
2005
2006
2007 2008
Max Drain Extension Sheet Resistance [Ohm/sq] (PMOS)
663
767
833
884
1739
Max Drain Extension Sheet Resistance [Ohm/sq] (NMOS)
310
358
389
412
811
Contact Silicide Sheet Resistance [Ohm./sq]
7.9
7.5
8.6
9.6
10
With shrinking device dimensions parasitic contact resistance
contribution to total device resistance will increase
-> Need to predict current-voltage characteristics & trans-conductance
of devices with this increased resistance values
Anna W. Topol, NGCM, September 2004
Research
Determination of Fundamental Physical Series Resistance Components
300
Limitations of Contact Scaling
For 90nm node geometries:
 Total extrinsic resistance is ~250 ohm-mm
~130 ohm-mm due to silicide contact resistance
Rco is dominant component
Rco ~50 % of Rtot > Rov > Rsp
 Need new materials & integration
solutions!!!
Resistance [ohm-mm]
250
200
150
100
50
0
0.4
0.8
Anna W. Topol, NGCM, September 2004
Vg
1.2
Research
Silicide Contact Scaling
 Benefits of salicide for high-performance CMOS devices
– Self-aligned process: selectively converts silicon regions into silicide
– Minimized silicide series resistance to intrinsic device
Ti, TiN cap
n+
C49 TiSi2
CoSi or NiSi
Ti, Co or Ni
n+
First anneal
and etch
n+
n+
C54 TiSi2,
CoSi2
Second anneal
n+
n+
 Bulk MOSFET technology limitations
– Silicide contained within S & D junction to prevent leakage path
– Silicide/Si junction to coincide with peak doping concentration of S/D
– Shallow junctions to suppress short channel effects (SCE)
 Silicon-on-insulator (SOI) MOSFET technology
– Reducing channel thickness suppresses SCE for both single- & double-gate
MOSFETs
– UTSOI channel -> thin Si in S/D regions to complete silicide formation
 Requires a revision of conventional salicide processes
Anna W. Topol, NGCM, September 2004
Research
Salicide Options for Various Generations
SILICIDE
C54-TiSi2
CoSi2
NiSi
Thin Film Resistivity ( mW-cm)
15-25
15-25
13-18
Schottky Barrier Height to n-Si (eV)
0.60
0.64
0.67
Formation Temperature ( ºC)
750-850
600-750
350-500
Si Consumed Normalized to Metal Thickness
2.3
3.6
1.8
Controlling Formation Mechanism
Nucleation
Nucleation/Diffusion
Diffusion
 C54-TiSi2
 CoSi2
− Difficult to transform in lines < 300 nm => increased contact
resistance
+ Only one disilicide crystal structure
+ Lower thermal budget
− Increased junction leakage due to rough interface
− High Si consumption (in lateral dimensions <100nm => limited
transformation)
− Co not compatible with SiGe technology, Ge not soluble in CoSi2
C. Lavoie, et al., J. ELECTRON. MATER. 31, 597-609 (2002).
C. Detavernier et al, PHYS. REV. B 62,12045 (2000), APPL. PHYS. LETT. 77, 3170 (2000)
Anna W. Topol, NGCM, September 2004
Research
New CoSi2 Process
50
52
X-ray diffraction map
Evolution of Co-silicide phases
as a function of temperature
(3 °C/s ramp)
Diffracted Angle 2 (deg)
54
56
58
60
a) Pure Co w/ Co2Si phase formed
within narrow temperature
window of ~ 20 °C
- vary with dopant
50
52
54
b) Co-Si mixture with Co2Si phase
window extends temperature
window by more than 100 °C
56
58
60
200
400
600
Temperature ( °C)
800
G. Cohen, et al., MAT. RES. SOC. SYMP. PROC. Vol. 686, p. 89, 2002.
Anna W. Topol, NGCM, September 2004
Research
Salicide Contact Scaling
 Metal Rich Si Alloys Based on Co2Si Process:
– Temperature window opens up to more than 100 °C
– Si in Co film reduces total silicon consumption by more than 10%.
– Low temperature formation occurs through Co diffusion (limits voiding)
– More uniform low resistance films
– With optimized surface preparation & anneal conditions up to ~20% Si
can be added to Co without causing bridging
 Advantages of NiSi
– Lower resistivity
– Lower Si consumption
– Compatibility w/ SiGe
Co
CoSi2
1
NiSi
Ni
1.3
3.5
For the same
Sheet Resistance
2.6
30-35 % saving on
Si consumption
Anna W. Topol, NGCM, September 2004
Research
Benefits of Lower Thermal Budget NiSi Process
 Diffusion controlled NiSi formation -> low roughness, limited bridging
Ni
RMS Roughness
0.4 nm
AFM Images
10mm x 10 mm
RMS Roughness
7.3 nm
n+
n+
Ni movement,
450°C annealed Ni -> NiSi
750°C annealed Ti -> TiSi2
 Limited number of vacancies in SOI or poly-Si
Ni diffusion:
Vacancies
in Metal Layer
Si diffusion:
Vacancies
in Si Layer
Christian Lavoie, ICMI, March 2004
Anna W. Topol, NGCM, September 2004
Research
100
10
1
200
1.E-02
1.E-03
-3
p+10Poly-Si
Poly-Si
n+
1.E-04
-4
10
Ni
(b)
p+ Poly-SiCo/Ti
Co-Ni/TiN
Co-Ni/Ti
Co/Ti
RCoW (W-mm)
1000
Junction Leakage (A/cm2)
Resistance (arb. units)
i2
Importance of
10-2 NiSi Process
Ni
(a)
-5
1.E-05
CoSiCoSi
2
10
2
1.E-06
-6
10
1.E-07
-7
10
1.E-08
-8
160
120
CoSi 2
80
40
10
Sub-100 nm As Junctions
NiSiNiSi
1.E-09
-9
10
PMOS
NiSi
0
300 400 500 600 700 800 900
300 400 500 600 700 800 900
55 60 65 25 30
30 35
35 40
40 45
45
50 55
55 60
60 65
65 25 30 35 40 45 50 55 60 65
50
RTP
Temperature
( oC)
RTP
Temperature
( ooC)
o
dth
Poly-SiGate
Gate
W
idth
Poly-Si
W
idth
Poly-Si
Gate
W
idth
RTP Temperature ( C)
RTP Temperature ( C)
 CoSi2 sheet resistance increases in narrow poly-Si gates
 NiSi has lower sheet resistance & lower thermal budget
– Avoids ~700 °C anneal => limits problems associated w/ dopant deactivation
AMD – MRS Spring 2003
Texas Instrument - IEEE Int. Electr. Dev. Meeting (2002).
Samsung – AMC 2000
Intel - IEEE Int. Electr. Dev. Meeting (2002)
IBM - C. Lavoie, et al., Silicide Technology for Future ULSI, edited by L.J. Chen, British IEE., 2004
Anna W. Topol, NGCM, September 2004
Research
Device Resistance Components Beyond 90nm Node
Rca
Device’s Resistance
Components:
- Silicide Contact Resistance: Rco
- Overlap Sheet Resistance (Rov)
- Spreading Resistance (Rsp)
Rca
Lcon
Spacer
Gate
Silicide
Ru,co
Rac,ov
R
spr,ov
dp,spRext,sp
Rsw,co R
Buried Oxide
Rsw,co R
R
R
R
dp,sp ext,sp spr,ov ac,ov
Ru,co
Rco
Rsp
- Increased Linkup Resistance
(Rlink-up)-> Metal plug/wire contact
resistance (local wiring)
Rov
Rtot  2 Rsd 2( Rco  Rsp  Rov )  R link up
Anna W. Topol, NGCM, September 2004
Research
Plug Contact Scaling Trends
Local Wiring Contact Schemes
Schematic cross-section of plug
a)
b)
 Resistance components degrade intrinsic device current
capabilities
Anna W. Topol, NGCM, September 2004
Research
25
(Arbitrary Units)
Contact Plug Resistance
Contact Plug Scaling Trend
21
17
13
9
5
1
130nm
90nm
65nm
Technology Node
45nm
Projected
 Projected resistance for 45nm node based on geometrical
parameters, assuming constant aspect ratio
Anna W. Topol, NGCM, September 2004
Research
Increased Plug Resistance: So What?
 The increased plug resistance translates directly into a
performance hit
– For 90nm technology, contact plug resistance accounts for
~2% performance degradation
– For 45nm technology, contact plug resistance is projected to
contribute to the degradation of circuit performance by 10%
 Need new material/process solutions to improve resistance of
the contact plug
Anna W. Topol, NGCM, September 2004
Research
Plug Scaling: Overview
Plug
dfill
 Dimensions (dPlug/hPlug)
fill
– Diameter and height scale
with each generation
tliner
liner
hPlug
dPlug
 Liner Material & Thickness (tliner)
– Liner acts as diffusion barrier layer & has higher resistance then fill
– Standard liner: Ti / TiN
 Fill Material & Diameter (dfill)
– Fill material needs to have low resistance & good fill properties
– Standard fill: CVD W
Anna W. Topol, NGCM, September 2004
Research
25
(Arbitrary Units)
Contact Plug Resistance
CA Scaling Trend: Possible Solutions
21
17
13
9
5
1
130nm
90nm
65nm
45nm
Technology Node
 Implementation of new material: plug resistance potentially
lowered dramatically
Anna W. Topol, NGCM, September 2004
Research
Contact Plug Dimension Scaling
IBM Capability to Demonstrate Creation of Small Plug Features
E-beam Written Plugs
Optically Written Plugs (SEM w/ Au coating)
= 267 nm
Nitride
Cap
= 219 nm
Silicide
 Good etch selectivity to nitride & silicide w/high (>84°) side wall angle
 Good plug size control of e-beam pattern (e-beam dose versus CD size)
Anna W. Topol, NGCM, September 2004
Research
Contact Plug Dimension Scaling
IBM Capability to Demonstrate Fill of <50nm Plugs
Lower resolution analysis (SEM)
Higher resolution analysis (TEM)
Metal
Wire
W
Plug
Gate
 Successful integration of plug level
− level alignment
− plug-gate spacing
 Good fill of up to 7:1 aspect ratio features
m
Anna W. Topol, NGCM, September 2004
Research
Contact Plug Scaling Trend
Contact Plug Resistance
(Arbitrary Units)
73
64
55
46
37
28
19
10
1
130nm
90nm
65nm
45nm
Technology Node
projected
 Projected vales versus experimental data for 45nm Node
Anna W. Topol, NGCM, September 2004
Research
Plug height 200nm
Plug height 300nm
1k
assuming 10nm void
assuming 5nm void
calculated R
100
10
H2FQDVGRX
Plug diameter
= 50nm bottom / 70nm top
H0FQDXGRX
H2FQDVGPC
1
H0FQDXGPC
(Arbitrary Units)
Contact Plug Resistance [W]
Electrical Data for 50nm CAs With Thin Liner
 Need best fill possible to increase metal contact area & decrease defects
Anna W. Topol, NGCM, September 2004
Research
Conclusions and Future Directions
 Contact Scaling Challenges
– Lithography: printing future generation patterns
– Integration + Materials: new CMOS-based device structures with novel
materials
– Performance: silicide and plug contact resistance increase
 Evaluation of Physical Limitations for Contact Scaling
– Resistance evaluation of silicide layer vs. size of the contact & silicide thickness
– Resistance evaluation of the plug contact vs. various contact sizes
• For different liner thickness and liner materials
• For different metal materials
• Introduction of ALD processes for conformal depositions
 Future Trends
– Pushing technology envelope beyond current “brick-wall” time-line estimates
– Introduction of novel (non-CMOS-based) devices & related material options
Anna W. Topol, NGCM, September 2004
Research