Transcript POL- SiP - Renesas e-Learning

ID 820C: Scalable Voltage Regulator(VR)
Renesas Electronics America Inc.
Tetsuo “Ted” Sato
Director, Business Development
13 October 2010
© 2010 Renesas Electronics Corporation. All rights reserved.
Version 1.0
Tetsuo “Ted” Sato
 Director Business Development
 Power Management Devices
 Standard Products
PREVIOUS EXPERIENCE:
 20+ years Mixed Signal IC design and management in Hitachi
 12 years Business Development in USA
 Member of IEEE Solid-State Circuit
 Member of Institute of Electronics Information & Communication
Engineers
 BSEE from Iwate University in Japan
 Received `2003 R&D 100 Awards
 `1998 IEEE IMS presented “Intelligent RF Power Module using
Automatic Bias Control system for PCS CDMA applications”
 100+ Patents in USA and Japan
2
© 2010 Renesas Electronics
Corporation. All rights reserved.
Renesas Technology and Solution Portfolio
Microcontrollers
& Microprocessors
#1 Market share
worldwide *
ASIC, ASSP
& Memory
Advanced and
proven technologies
Solutions
for
Innovation
Analog and
Power Devices
#1 Market share
in low-voltage
MOSFET**
* MCU: 31% revenue
basis from Gartner
"Semiconductor
Applications Worldwide
Annual Market Share:
Database" 25
March 2010
** Power MOSFET: 17.1%
on unit basis from
Marketing Eye 2009
(17.1% on unit basis).
3
© 2010 Renesas Electronics
Corporation. All rights reserved.
Renesas Technology and Solution Portfolio
Microcontrollers
& Microprocessors
#1 Market share
worldwide *
ASIC, ASSP
& Memory
Advanced and
proven technologies
Solutions
for
Innovation
Analog and
Power Devices
#1 Market share
in low-voltage
MOSFET**
* MCU: 31% revenue
basis from Gartner
"Semiconductor
Applications Worldwide
Annual Market Share:
Database" 25
March 2010
** Power MOSFET: 17.1%
on unit basis from
Marketing Eye 2009
(17.1% on unit basis).
4
© 2010 Renesas Electronics
Corporation. All rights reserved.
Renesas Power Management
Devices and Solutions
Scalable Multi-SiP Solution




Compact and Integrated SiP
 8x8 and 6x6 Package integrates PWM, Driver,
HS+LS FET
 Capable to 40A; peak efficiencies reach 94%
 Networking/Computing main board 12 or 19Vin to
0.6 to 3Vout
Performance Package
Value Package
Hybrid Analog/Digital VR control
Fully scalable, 2 rails up to 6 phase, 180A total
Super efficiency from 1% to 100% of full load
CPU & GPU for Server, Workstation, and NBPC
Integrated
 For best efficiency in high current applications
 Up to 175°C and 180A Id
 Industrial, Automotive, Telecom, DC-DC Module
 Leadless, SO-8 footprint compatible
Thin-Profile Package
 Al Ribbon Bonding supported to lower
package resistance and cost
 PC/Server and Mobile Applications
 Industry-Standard Package
Standard Package
5
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Corporation. All rights reserved.
 Low cost
 General Purpose for non-isolated DC-DC
Discrete
Renesas Power Management
Devices and Solutions
Scalable Multi-SiP Solution




Compact and Integrated SiP
 8x8 and 6x6 Package integrates PWM, Driver,
HS+LS FET
 Capable to 40A; peak efficiencies reach 94%
 Networking/Computing main board 12 or 19Vin to
0.6 to 3Vout
Hybrid Analog/Digital VR control
Fully scalable, 2 rails up to 6 phase, 180A total
Super efficiency from 1% to 100% of full load
CPU & GPU for Server, Workstation, and NBPC
Integrated
Scalable Multi-SiP Solution
Highly efficient, hybrid analog/digitally
controlled, fully scalable
VR solution
 For best efficiency in high current applications
for
high-current
applications
Performance Package
 Up to 175°C and 180A Id
 Industrial, Automotive, Telecom, DC-DC Module
Value Package
 Leadless, SO-8 footprint compatible
Thin-Profile Package
 Al Ribbon Bonding supported to lower
package resistance and cost
 PC/Server and Mobile Applications
 Industry-Standard Package
Standard Package
6
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Corporation. All rights reserved.
 Low cost
 General Purpose for non-isolated DC-DC
Discrete
Innovation
Variable Cylinder Management (VCM)
Cylinder Banks used only when needed
Cleaner Emissions
+
Energy Savings
7
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Corporation. All rights reserved.
Our Scalable Solution
Renesas provides a flexible solution for managing high-current
applications which maximizes efficiency by intelligently
managing power to the various system rails. Much like
individual cylinders are activated and de-activated in the
Variable Cylinder Management engine technology, banks of
single packaged Point-of-Load (POL) devices are turned on and
off depending on the system’s power requirement for each of
the power rails at any given time.
8
© 2010 Renesas Electronics
Corporation. All rights reserved.
Agenda
 What is POL-SiP (point-of-load system-in-package)?
 Scalable VR Concept and Architecture
 Advantages of MCU Control and POL-SiP Devices
 System Sensing, Monitoring, and Control
 Overview of EVB and Software Control through GUI
 Lab
 System bring-up
 Programming through GUI
 System monitoring and control
9
© 2010 Renesas Electronics
Corporation. All rights reserved.
Key Takeaways
By the end of this session you will be able to:
 Understand POL-SiP concept
 Understand 1-phase, 2-phase VR system by POL-SiP
 Understand Scalable VR concept & architecture
 Understand Scalable VR advantages
 Identify appropriate applications for Scalable VR
10
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■ What is a POL-SiP ?
All silicon chips for a Buck Converter in one package!
VIN
Top MOS FET
External L&C
PWM Control
& Gate Drive
VOUT
Bottom
MOS FET
+ SBD
(Schottky Barrier Diode)
3 chips in ONE package!
Control IC + Top MOS + Bottom MOS =
11
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8mm x 8mm QFN-56
■ Why POL-SiP ?
1. Large scale Logic IC power requires Low Voltage and High Current
Icc
DCDC
converter
Vin
20W
Load ( IC )
Vcc
25
If a 20W load is used, then the
20
Low Voltage and
High Current
Icc (A)
current increases and the voltage
decreases
I = P/V
15
10
5
0
5
4
3
2
1
Vcc (V)
High current density devices are required!
12
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Corporation. All rights reserved.
POL-SiP
0
■ Why POL-SiP ?
2. The Vcc range of Large Scale Logic ICs is becoming increasingly narrow
6
Core voltage (V)
5
4
500mV
(0.5um)
250mV
(0.22um)
3
300mV
(0.35um)
2
100mV
(65nm)
1
0
0.6
0.5
0.4
0.3
0.2
0.1
0
Process Rule (um)
Fast response converters are required
POL-SiP
Peak Current Control Mode
13
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Corporation. All rights reserved.
■ Features of Renesas POL-SiP(R2J20702NP)
 Huge current
Up to 40A output current per device.
For even higher currents:
Easy and
Simple
 High efficiency
2-phase operation, Current sharing
Synchronous operation, Tracking-start
92.5% @Vin=12V, Vout=1.8V, Fsw=500kHz
Peak current mode topology
 Fast response
for transient load Output voltage fluctuation range is 40mV or below
(di/dt=50A/us, 4.5A step)
 Useful functions
14
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Over current protection ( Hiccup )
Remote ON/OFF control
■ Experimental Data of POL-SiP
 Efficiency & Surface Temperature of the Package
Conditions
Vin=12V, Vout=1.8V, fsw=500kHz, L=0.32uH, Cout=600uF, No Air Flow
95
94
93
92
91
90
89
88
87
86
85
0
15
R2J20702NP
P K G S urf ac e Temp (C)
E f f ic ienc y (% )
R2J20702NP
5
10
15
20 25
30
Output Current (A)
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35
40
120
110
100
90
80
70
60
50
40
30
20
0
5
10 15 20 25 30
Output Current (A)
35
40
■ Experimental Data of POL-SiP
 Transient response
Conditions
Vin=12V, Vout=1.8V, fsw=468kHz, L=0.32uH, Cout=600uF
Iout : 0A <=> 4.5A,
Iout slope : 50A/us
Iout : 0A to 4.5A
Iout : 4.5A to 0A
30mV
Vout(AC)
(50mV/div.)
Vout(AC)
(50mV/div.)
Time (40us/div.)
16
30mV
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Time (40us/div.)
■ Various Parallel Operation of POL-SiP
SW node1
 2-phase operation
40A
SW node2
80A
Iout up to 80A max
Current Sharing
IL1
180° Phase-shifted
synchronization
40A
Inductor
Current
IL1
IL2
IL2
 Multi-channel operation (ex. 2 channel
operation)
ex. 2.4V
ex. 1.5V
Synchronous operation
(up to 5ch available)
Tracking start
Ratiometric
Vout1
Vout2
Coincident
Vout1
Vout2
17
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Corporation. All rights reserved.
■ Evaluation Boards of POL-SiP
 Single phase EVB
 2 phase EVB
Default conditions
Vin= 12V
Vout= 1.8V
Adjustable
Iout= 20A max.
fsw= 500kHz
Default conditions
Vin= 12V
Vout= 1.8V
Adjustable
Iout= 42A max.
fsw= 450kHz / phase
R2J20702
 2 channel EVB
Default conditions
Adjustable
Vin= 12V
Vout_1= 2.5V / Vout_2= 1.8V
Iout_1= 23A / Iout_2= 21A max.
fsw= 480kHz /channel
R2J20702
R2J20702
18
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Corporation. All rights reserved.
■ Design
tool
 Design guide for loop
compensation.
(EXCEL sheet)
Enter into the red framed cells
obtain constants for
loop compensation
19
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Corporation. All rights reserved.
■ Block diagram
ON/OFF
REG5
DRV5
BOOT
VCIN
SBD
5V (4%)
Regulator
ON / OFF
Supervisor
IREF
Reference
Current
Generator
5.25V (4%)
Regulator
VIN
UVLO
8V to 16V
REG GOOD
CT
OSC
50ns
SYNC
Id
h
Active
Current
Sensing
Max.
Duty
RES
RES
Pulse
Generator
(Bilateral)
55ns
Blanking
Max.
Duty
REG GOOD
VOUT
ON / OFF
PWM
R Q
EO
S
Q
REG5
0.6V(1%
)
Error Amp.
REG5
Idh
22000
OCP
Gate
Drive
Logic
Circuit
SW
DRV5
TRK-SS
ON / OFF
REG GOOD
OCP
Current
Sense
Comparat
or
1.5V
50k
VOUT
FB
0.1V
OCP
Comparator
50k
490uA
SGND
20
OCP
Hiccup
Control
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Corporation. All rights reserved.
Ishare
RAMP
CS
(1024 pulses
blank)
PGND
■ ACTIVE CURRENT SENSING
REG5
ON/OFF
DRV5
BOOT
VCIN
SBD
ON / OFF
5V (4%)
Regulator
Supervisor
IREF
Reference
Current
Generator
CT
Active
Current
Sensing
55ns
Blanking
Max.
Duty
RES
50ns
SYNC
RES
Pulse
Generator
(Bilateral)
Max.
Duty
REG GOOD
Q
REG5
0.6V(1%)
Error Amp.
REG5
VOUT
ON / OFF
PWM
S
8V to 16V
Id
h
R Q
EO
VIN
UVLO
0.6V(1%)
REG GOOD
OSC
5.25V (4%)
Regulator
Idh
22000
OCP
Gate
Drive
Logic
Circuit
SW
DRV5
TRK-SS
ON / OFF
REG GOOD
OCP
Current
Sense
Comparator
1.5V
50k
VOUT
FB
0.1V
OCP
Comparator
50k
490uA
SGND
21
OCP
Hiccup
Control
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Corporation. All rights reserved.
Ishare
RAMP
CS
(1024 pulses
blank)
PGND
■ ACTIVE CURRENT SENSING
Wave Form
Vin=12V, Vout=1.8V, Freq=469kHz, L=440nH, Cout=600uF, Rcs=410ohm
Iout=0A
Iout=10A
Iout=20A
SW voltage
(10V/div)
CS voltage
(0.5V/div)
Coil current
(10A/div)
500ns/div.
500ns/div.
500ns/div.
The peak voltage of CS pin is proportional to coil current
22
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Corporation. All rights reserved.
■ Peak Current Control Mode
Item
Voltage mode
Peak current mode
Loop analysis
easy
somewhat easy
Loop compensation
somewhat complicated
simple
Transient response
slow
fast
Noise immunity
good
good
somewhat complicated
very easy
difficult
very easy
Ext synchronization
Current sharing
Peak current mode = Big advantage
23
© 2010 Renesas Electronics
Corporation. All rights reserved.
Agenda
 What is POL-SiP (point-of-load system-in-package)?
 Scalable VR Concept and Architecture
 Advantages of MCU Control and POL-SiP Devices
 System Sensing, Monitoring, and Control
 Overview of EVB and Software Control through GUI
 Lab
 System bring-up
 Programming through GUI
 System monitoring and control
24
© 2010 Renesas Electronics
Corporation. All rights reserved.
ANALOG
DIGITAL
HYBRID
■ Outline of the system
Alert#
CLK
DATA
Integrated Power SIP
R2J20702NP
I2C
Phase shifted clock
(Not PWM signals)
Input source
Microprocessor
R8C/3GA
VCC
Error amplifier
LOAD
Error voltage
DAC set
voltage
Remote sensing buffer
25
© 2010 Renesas Electronics
Corporation. All rights reserved.
Voltage feedback
■ Concept of RENESAS Multi-phase VR
by POL-SiP
4-phase example
No “PWM” signals fed to POL-SIPs, only need phase shifted clock signals.
Each POL-SIP is like a cylinder in VCM, MCU adds or sheds POL-SIPs to
optimize load efficiency or performance as required
Clock-1
Clock-2
From
MCU
Clock-3
Clock-4
Error Voltage Bus
Error Amp.
26
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POL- SiP (8x8mm, QFN56)
(Not a DrMOS),
includes ACS(Active Current Sensing)
and PWM modulator.
Agenda
 What is POL-SiP (point-of-load system-in-package)?
 Scalable VR Concept and Architecture
 Advantages of MCU Control and POL-SiP Devices
 System Sensing, Monitoring, and Control
 Overview of EVB and Software Control through GUI
 Lab
 System bring-up
 Programming through GUI
 System monitoring and control
27
© 2010 Renesas Electronics
Corporation. All rights reserved.
■ Key Highlights of RENESAS Hybrid Power Solution
 Digital interface to host CPU
- I2C
- Vout control, status report, etc.
 Design flexibility
- GUI
 Fast transient response
- Analog PWM (Peak current mode)
- Output current sensing built-in
 Efficiency Boost
- Copper Clip Bonding
- New SBD JET MOSFET built-in
 Eliminates need for PWM control IC
28
© 2010 Renesas Electronics
Corporation. All rights reserved.
ANALOG
DIGITAL
HYBRID
New  R8C/3GA
Microcontroller
Technology
Integrated Power SIP
Technology
New  R2J20702NP
■ What’s NEW of Renesas Scalable VR solution
Tiny MCU (R8Cxx)
• Serial Interface to main CPU
• VR master control (VID, Phase)
• Monitors (Io, Vo, Temp, etc)
• Adaptive Control by S/W
• High resolution Calibration
29
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POL-SiP (R2J20702NP)
• VR slave driving
• High Power Up to Io=40A/ch
• High Efficiency
• High fpwm Up to 1MHz
• Current sensing built-in
Agenda
 What is POL-SiP (point-of-load system-in-package)?
 Scalable VR Concept and Architecture
 Advantages of MCU Control and POL-SiP Devices
 System Sensing, Monitoring, and Control
 Overview of EVB and Software Control through GUI
 Lab
 System bring-up
 Programming through GUI
 System monitoring and control
30
© 2010 Renesas Electronics
Corporation. All rights reserved.
■ RENESAS Scalable VR by POL- SIP
 An example of a conventional V-mode controlled buck converter
Vin
PWM Signal
PWM
Control
Circuitry
PWM Signals
For other phases
Vcc
Driver
LOAD
Current information
Voltage
feedback
- Difficult to use a digital interface.
- Complex PWM circuit required as phase number increases.
 Analog Digital Hybrid, C-mode controlled buck converter
Vin
Clock pulse
Pulse generate,
Analog error amp.,
Circuitry
Voltage
feedback
Phase shifted clock
For other phases
Error voltage bus
(Current information)
Easy to accomplish with an MCU
and simple analog components.
31
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Current sense,
PWM control,
and Drive
ANALOG
DIGITAL
HYBRID
Vcc
LOAD
POL-SIP product.
Integrated
Power SIP
P/N : R2J20702NP
■ RENESAS Scalable VR by POL- SIP
 Voltage Mode
(Conventional)
Generated PWM signal compared with
Triangle wave and Error Voltage
Triangle wave
 Peak Current Mode
(Proposed)
Generated PWM signal compared with Choking Coil
Current and Error Voltage
Error Voltage
Error Voltage
Clock
Choking Coil
Current by ACS
PWM
PWM
PWM Comparator
Feedback Voltage
Feedback Voltage
Error Amp
PWM
Reference Voltage
Triangle Wave
32
PWM Comparator
S
Q#
Error
amp
R
Reference Voltage
Choking Coil
Current
PWM
Clock
Need current sensing circuit for overcurrent protection, light load control and
current balance
ACS for Peak Current Mode Control, OCP,
L/L control and current sharing
Slow response
Fast response
© 2010 Renesas Electronics
Corporation. All rights reserved.
■ RENESAS Scalable VR by POL- SIP
 DCR Sensing
(Current)
Detect Output current using voltage drop of choking coil
 Active Current Sensing
(Original)
Detect Output current using Sensing MOSFET in POL-SIP
POL-SIP
Driver+FETs
PWM IC
Clock
PWM
MCU
Current
Signal
ACS
PTC
Current sense
33
Poor accuracy
High Accuracy (+/-5%)
Large Temperature dependency
No Temperature dependency
Difficult to use small DCR choking coil
Can use small DCR choking coil
Larger PCB space required
Less PCB space required
Higher PCB thermal resistance
Lower PCB thermal resistance
Possible destruction of high side FET
High side FET never blows up
© 2010 Renesas Electronics
Corporation. All rights reserved.
■ RENESAS Scalable VR by POL- SIP
 DCR Sensing
 Active Current Sensing
(Current)
ACS deviation=+/-5%
Driver+FETs
PWM IC
DCR=0.4mohm+/-8%
Clock
PWM
MCU
L+Rdc
Current sense Amp
Gain deviation=+/-3%
Rcs Ccs
(Original)
Current
Signal
ACS
PTC
Rex=470ohm+/-1%
Current sense Input Offset = +/-1mV
In this example, DCR Sensing
does NOT consider:
Iout Accuracy Target (2-phase)
DCR
ACS
45-60A (typical)
Iout Accuracy (%)
80
DCR Temp dependency
70
60
NTC (thermistor) mismatching
DCR Sensing
50
sL/Rdc, sRcsCcs mismatching
40
30
Noise interference
20
10
ACS Sensing
0
0
20
40
60
VR Load (%)
34
© 2010 Renesas Electronics
Corporation. All rights reserved.
80
100
120
If these items were considered, the
accuracy would be worse.
POL-SIP
Agenda
 What is POL-SiP (point-of-load system-in-package)?
 Scalable VR Concept and Architecture
 Advantages of MCU Control and POL-SiP Devices
 System Sensing, Monitoring, and Control
 Overview of EVB and Software Control through GUI
 Lab
 System bring-up
 Programming through GUI
 System monitoring and control
35
© 2010 Renesas Electronics
Corporation. All rights reserved.
■ Example 1: Scalable VR 6-phase VR Evb
MCU
R8C/2A
6-phase VR
36
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■ Example 1: Scalable VR 6-phase VR Block Diagram
Vin_12V
6-Phase VR
POL-SiP1
Enable2
Phase Control2
Voltage Control
POL-SiP2
LOAD
VSENSE
Enable1
Phase Control1
Voltage Control
Master
MCU
37
I2C,
SMBus,
PMBus
VRM MCU
(R8C/2A)
© 2010 Renesas Electronics
Corporation. All rights reserved.
…
…
Enable6
Phase Control6
Voltage Control
POL-SiP6
VID Monitor
Temperature
Output Current1
VLOCAL
VPROTECT
(Io=150A)
■ Example 1: Scalable VR 6-phase VR Result
Master MCU R8C/2A + Slave POL-SiP R2J20702NP x6
VIN=12V
VOUT=1.2V
6-phase
fPWM=540KHz
300LFM Airflow
No heatsink
6-Phase Efficiency (%)
100
Efficiency (%)
90
80
70
60
Efficiency(%)
50
150
140
130
120
110
© 2010 Renesas Electronics
Corporation. All rights reserved.
100
38
90
80
70
60
50
40
30
20
10
0
IOUT (A)
■ Example 2: Scalable VR 4-phase VR Evb
ANALOG
DIGITAL
HYBRID
+12V input
+5V input (for MCU)
I2C port
LCD interface port (optional)
I2C ~ RS232 interface circuitry
VR
1.5V (80A)
RS-232C
LOAD
PC
39
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Corporation. All rights reserved.
■ Example 2: Scalable VR 4-phase VR Block Diagram
Alert#
CLK
DATA
ANALOG
DIGITAL
HYBRID
Integrated Power SIP
R2J20702NP
I2C
Phase shifted clock
(Not PWM signals)
Input source
Microprocessor
R8C/3GA
VCC
Error amplifier
LOAD
Error voltage
DAC set
voltage
Remote sensing buffer
40
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Corporation. All rights reserved.
Voltage feedback
■ Example 2: Scalable VR 4-phase VR Specification
 Four phase VR in 2.5” x 1”
ANALOG
DIGITAL
HYBRID
 Power Spec.
•
•
•
•
•
•
Vin = 12V typical
Vout = 1.5V
Iout = 80A
Freq = 500kHz
Efficiency >90% @ 80A
Load step +/-2.5% @ 30A step,
30A/us
• Ripple voltage 15mVpp
1 inch
2.5 inch
 Graphic interface
• RS232C
• Adjustable: Vout, Freq, Number of
phases
• Monitor: Vin, Vout, Iin, Iout, Temp
• Protection: OVP, OCP, OTP
 I2C serial communication
41
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Back side
POL-SIP
ANALOG
DIGITAL
HYBRID
■ Example 2: Scalable VR 4-phase VR Efficiency
Condition; Vin=12V, Vo=1.5V, Freq=500kHz
Efficiency vs. Load current
92
Efficiency（%）
91
90
89
88
87
SheddingNoAirflow
SheddingAirflow
86
85
0
10
20
30
40
50
60
Load current（A)
42
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70
80
90
100
ANALOG
DIGITAL
HYBRID
■ Example 2: Scalable VR 4-phase VR Efficiency
Condition; Vin=12V, Vo=1.5V, Freq=300kHz and 500kHz
Airflow=300LFM
Efficiency vs. Load current
93
92
Efficency(%)
91
90
89
88
Fsw=500KHz
Fsw=300KHz
87
86
85
0
10
20
30
40
50
60
Output current(A)
43
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Corporation. All rights reserved.
70
80
90
100
ANALOG
DIGITAL
HYBRID
■ Example 2: Scalable VR 4-phase VR PKG Temp.
Condition; Vin=12V, Vo=1.5V, Freq=500kHz
Package temperature vs. Load current
100
Temperature（degC）
90
80
70
60
50
40
30
20
SheddingNoAirflow
10
SheddingAirflow
0
0
10
20
30
40
50
60
Load current（A)
44
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70
80
90
100
■ Example 2: Scalable VR 4-phase VR Output Ripple
Condition; Vin=12V, Vo=1.5V, Freq=500kHz
2phase 20A
10mV/div
10mV/div
1phase 10A
15mVpp
6mVpp
1µs/div
1µs/div
4phase 80A
10mV/div
10mV/div
4phase 40A
7mVpp
1µs/div
45
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6mVpp
1µs/div
ANALOG
DIGITAL
HYBRID
■ Example 2: Scalable VR 4-phase VR Load Transient
Condition; Vin=12V, Vo=1.5V, Freq=500kHz, Io=0-30A(30A/us)
Load freq.=10kHz
50mV/div
50mV/div
Load freq.=1kHz
76mVpp
68mVpp
100µs/div
50µs/div
50mV/div
58mVpp
5µs/div
46
Load freq.=500kHz
50mV/div
Load freq.=100kHz
© 2010 Renesas Electronics
Corporation. All rights reserved.
30mVpp
2µs/div
ANALOG
DIGITAL
HYBRID
ANALOG
DIGITAL
HYBRID
■ Test environment for load transient test
The wires should be as short as
possible so that minimize parasitic
inductance.
Electrical Load
(Keisoku-Giken)
Probe
+5V input
47
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+12V input
To DMM
■ GUI (Graphic User Interface) … Controlled by PC
+12V input
+5V input (for MCU)
I2C port
LCD interface port (optional)
I2C ~ RS232 interface circuitry
VR
(2” x 1”)
GUI
1.5V (80A)
LOAD
RS-232C
PC
648
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Corporation. All rights reserved.
■ GUI (Graphic User Interface) … setting parameters
649
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Corporation. All rights reserved.
■ GUI (Graphic User Interface)
650
© 2010 Renesas Electronics
Corporation. All rights reserved.
… VR operating
■ GUI (Graphic User Interface)
651
© 2010 Renesas Electronics
Corporation. All rights reserved.
… OCP example
■ GUI (Graphic User Interface)
… real time monitor
OVP level
VOUT monitor window
OCP level
IOUT monitor window
Temperature monitor
window
652
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Corporation. All rights reserved.
Agenda
 What is POL-SiP (point-of-load system-in-package)?
 Scalable VR Concept and Architecture
 Advantages of MCU Control and POL-SiP Devices
 System Sensing, Monitoring, and Control
 Overview of EVB and Software Control through GUI
 Lab
 System bring-up
 Programming through GUI
 System monitoring and control
53
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Corporation. All rights reserved.
Questions?
 What are the merits of an integrated solution, such as
Renesas POL-SiP, versus a discrete solution?
 Why is scalability important for VR design?
 What are some advantages of Active Current Sensing(ACS)?
 Audience Questions?
54
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Corporation. All rights reserved.
Our Scalable Solution
Renesas provides a flexible solution for managing high-current
applications which maximizes efficiency by intelligently
managing power to the various system rails. Much like
individual cylinders are activated and de-activated in the
Variable Cylinder Management engine technology, banks of
single packaged Point-of-Load (POL) devices are turned on and
off depending on the system’s power requirement for each of
the power rails at any given time.
55
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Corporation. All rights reserved.
Thank You!
56
© 2010 Renesas Electronics Corporation. All rights reserved.
Renesas Confidential
Appendix
57
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Renesas Confidential