Transcript Ch.8 Layout Verification

Ch.8 Layout Verification
TAIST ICTES Program
VLSI Design Methodology
Hiroaki Kunieda
Tokyo Institute of Technology
8.1 DRC/LVS
Layout Design
Netlist
Layout Design
Functional Verification
ATPG
Test
Pattern
Layout
Netlist
Gate Level Simulatior
Mask Data
DRC/LVS
DRC & LVS
[Objective]
to check design rule violation by DRC CAD (Design Rule Checker) and to
check validity of layout by LVS CAD (Layout versus Schematic).
[Method]
1. DRC uses computational geometry to check relation of overlap or
distance between polygons of either the same or the different layers.
2. LVS uses schematic derived from layout result to compare components
and connections between original schematic and derive one.
[Problem]
1. Reduction of scan path flip flops
2. Speed up of testing such as concurrent testing
Lａｙｏｕｔ Design 4
DRC (Design Rule Checker)
Design Rule
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Problems when wire are
too wide or narrow.
Polysilicon should
extend beyond
boundary of difusion
area.
The cut of via must
connect elements and
not mistakenly connect
to substrate or others.
SCMOS Design Rules
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Metal1 min-width=3λ,
min-sep= 3λ
Metal2 min-width=3λ,
min-sep= 3λ
poly
min-width=2λ,
min-sep= 2λ
n, p-dif min-width=3λ,
min-sep(n-n, p-p)=3λ (n-p10λ)
Tube
min-width=10λ,
min-distance(tub-active)= 5λ
Transistors min-W/L=3λ/2λ poly
extension= 2λ
dif extension= 2λ
active-poly/metal via=λ
min-sep(tran.-tran.)= 2λ
min-sep(tran-tub.tie) = 3λ
SCMOS Design Rules
(continue)
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Vias
cuts=2λx2λ
via =4λx4λ
n,p.diff-poly, poly-metal1
n,p.diff-metal1,
metal1-metal2
Tub ties cuts =2λx2λ
metal =4λx4λ
Metal1 min-width=6λ,
min-sep= 4λ
available via to metal2
Special rules
cut to poly – poly sep =3λ
poly.cut-dif.cut sep=2λ
cut-tran.active sep =2λ
dif.cut-dif sep = 4λ
meta2.via must not be directly
over polysilicon
Prohibit small negative features.
Mask Pattern Analysis
Clock wise direction for outer boundary
Anti-clock wise direction for inner boundary
Logic Operations
OR
SuB
AND
ExOR
8.2 Post Layout Simulation
Circuit Extraction
Basic Operation of Circuit Extraction
NOT, AND, OR between 2 masks
grow and shrink operation over masks.
1) extraction of transistors
AND(poly - p/n.diff)
2) identify via
grow cut
AND(grown-cut, metal, poly)
Transistor Parasitics
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Cg: gate capacitance
= 0.9fF/μm2 (2 μprocess)
Cgs/Cgd: source/drain overlap capacitance
=Cox W (Cox: gate/bulk overlap
capacitance)
Wire Parasitics
Junction capacitance
Cj0 = εSi/xd = Cjo/[sqrt(1+Vr/Vbi)]
Depletion region capacitance
Cj0 : zero-bias depletion capacitance
εSi : permittivity of silicon
xd : thickness of depletion region
depending on applied voltage.
Plate and fringe MOS capacitance
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Plate capacitance
per unit area assumes
infinite parallel plates.
A fringe capacitance
per unit perimeter
must be added to take
into consideration of
the changes in
electrical field at the
edges.
metal
3
0.1fF/cm2
0.3fF/cm2
(overlapping area)
Depending on distance
Resistance Measurement
Ohms per square
[Ω/ ]
= Sheet resistance
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0.5 μm process (λ=0.25 μm)
1) Polysilicon resistance
Rpoly=[18/3]x4[Ω/ ]=24 Ω
2) n-diffusion resistance
[(9/3)+(6/3)+1/2]x
2 [Ω/ ]=11 Ω
8.3 Test
Lａｙｏｕｔ Design 5
ATPG (Test Pattern Generation)
[Objective]
to generate test patterns to test IC after fabrication.
[Method]
D algorithm is used to generate test patterns, automatically.
to prove coincidence of logic functions between HDL description
and logic gate circuit.
[Problem]
1. Reduction of scan path flip flops
2. Speed up of testing such as concurrent testing
Ｌｏｇｉｃａｌ Ｆａｕｌｔ Ｍｏｄｅｌ
1. Stuck-at-0/1 Fault model : Logic
2.
3.
4.
5.
value of wire segment is stuck at
either logic 0 or logic 1.
Single Fault: only one fault happens
for each sample.
Fault Test: logic circuit is tested by
inserting various test input vectors
and by observing its output, to check
whether any single fault at each wire
segment does not occur.
ATPG: Automatic Test Pattern
Generator is a CAD software to find
out necessary input test vectors.
Tester: in manufacture factory,
tester is implemented so as to check
volumes of chips in a short time,
automatically.
Fault Difference Function
d(x)= H(x) [g(x, 1) ? g(x, 0)]
Test vectors, satisfying
1. to drive 1 at wire with stuck
at 0 fault
d(x)
2. to set D, which is either 0 at = f(x)?f0(x)
fault or 1 at normal.
= H(X)g(x, H(x)) ? g(x, 0)
3. to transmit D to the output = H(x)’g(x, 0) ? H(x)g(x, 1) ? g(x, 0)
= H(x)g(x, 1) ? (H(x)’? 1)g(x, 0)
= H(x) [g(x, 1) ? g(x, 0)]
D Algorithm
1. For stuck-at-fault 0, find out
condition of inputs to set up 1.
2. Set D at the wire.
3. Decide wire logic values for D to
be transmitted to output.