Transcript Manufacturing Flow Overview

EEE-287
California State University
Sacramento
VLSI Design IC Manufacturing and Test
Instructor: Tony Osladil
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Tony Osladil
Manufacturing Flow Overview
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(Typical flow - variations exist)
Purchase Blank Wafers
Wafer Processing
E-Test
Wafer Sort
Assembly
Burn In (BI)
Class Test
Inspect, Mark & Pack
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Purchase Blank Wafers
• Current Technology is 8” (diameter)
– 6” still in volume production
– 12” in early production ramp (not all companies)
• Number of die goes up with square of radius (pr²)
– 6” to 8” wafer is a 78% area increase.
– Center die to edge die ratio also improves
• Cost of material (gasses, etc.) little to no increase.
• Difficulty is in consistency across large wafers.
– Photoresist, CVD (deposition) and thermal consistency.
– 12” wafers are reaching limits of human handling.
• Wafers purchased, due to low level of proprietary content.
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Wafer Processing
• Defines all silicon structures
– Transistors, Resistors, Capacitors in Si and SiO2
– Known in fabrication plants as “front end” processing
• Defines metalization for interconnect
– Known in fabrication plants as “back end” processing
Key Attributes
– Leff
– Tox
– Metal Quality (line width, metal stringers)
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E-Test
• Fabs need a way of monitoring processing
consistency regardless of product being made.
• Numerous simple test structures placed in scribe
line (N channel FET, resistor, etc.)
• Allows measurement of critical electrical
parameters on each wafer with same test hardware
and software (Vt, IDsat, BV, rho, etc.)
• Scrap limits are set to guarantee consistency.
• Trends in fab readily detectable.
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Wafer Sort
• Utilizes a probecard with needles to contact bond pads.
• ATE (Automatic Test Equipment) testers utilized.
– Similar in concept to bench equipment driven by HPIB.
– Power supplies, volt/ammeters, vector drive/compare logic
– Test vectors are logical 0’s and 1’s applied to device inputs and
compared to device outputs.
• Essentially, a truth table for the device.
• Used to screen out bad die before wrapping an expensive
package around them.
• Not all test are done at wafer sort.
– AC values not accurate (L and C of package affect timing).
• May be done at hot temperature using a “Hot Chuck”
• Bad die receive an ink dot, usually at an Off-line Inking
station.
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Assembly
Mount and saw.
– Saw cuts through wafer but not through plastic film.
– Saw blade cuts away approximately 2 mils of silicon
• Die Attach to leadframe or substrate using silverfilled adhesive or solder.
– Provides mechanical, electrical and/or thermal connection to
leadframe.
• Wirebond.
– Gold wire attached by
ultrasonic thermal bonding.
– “ball” bond on die pad,
– “wedge” bond on leadframe
• Solder balls on pads
replace wirebond for
“flip-chip” assy
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Tape-BGA
Au Wire
Die Attach Paste
Encapsulation (Mold)
Tape
Solder Resist
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Solder Ball
Assembly (cont.)
• Mold
– Plastic (epoxy cresol novolac polymer) is injection
molded to encapsulate die and wires.
– Wire sweep is largest threat at this stage.
• Tends to be limiting factor for max wire length.
– Ceramic packages receive a metal or ceramic lid instead
of plastic mold injection.
• Plate, Trim and Form
– Leadframe is plated with gold or tin to reduce corrosion
and increase solderability.
– Leadframe is cut away from carrier.
– Leads are formed into final shape.
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Package Evolution
• As transistor density has allowed integration
of more functions (requiring more I/O’s),
package pincount has increased.
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DIP (Dual In-line Package)
PLCC (Plastic Leaded Chip Carrier)
QFP (Quad Flat Pack)
BGA (Ball Grid Array)
• Many variations on these packages exist.
– PGA (Pin Grid Array), TSOP (Thin Small
Outline Package), etc.
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Burn-In
• Activates latent failures due to manufacturing
defects
– Oxide or silicon crystalline defects
– Diffusion of unintended impurities (e.g. sodium)
– Metal electromigration or bridging.
• High temperature and voltage provide activation
energy to accelerate defects.
– Voltage = Vcc x 1.25 or more, Temp = 125C typ.
– Defect degradation is chemical effect, chemical
processes occur faster with more energy.
• Toggle coverage is important to provide voltage
stress across all junctions.
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Burn-In (cont.)
• Takes advantage of the “bathtub curve”
– Majority of failures in first 10-20 years of life occur in
first 50 hours of use or less (“infant mortality”).
– Equivalent activation energy to ~50 hours of normal
life can be applied in ~6 hours or less of Burn-In (BI).
• Exact acceleration is dependent on defect type and process
technology.
• Limitations to temperature and voltage
– Degradation (glass transition) temperature of mold
epoxy
– Breakdown voltage of transistors.
• BI is a stress, not a test
– Testing is needed after BI to detect activated failures
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Class Test (aka Final Test)
• Eliminates assembly defects and defects activated
at BI.
• Used to separate devices into performance classes
– Example: Test at 300MHz. If fail, test at 266MHz.
– Tested at room, hot and cold.
– AC Parametric screen includes package effects
• Capacitive slowdown, Inductive supply bounce
• ATE (Automatic Test Equipment) testers utilized.
– Applies test vectors to test the device’s function
– Voltmeters and ammeters are used to test DC
parameters
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Class Test (cont.)
• Hot test is usually most critical since speed is key
differentiator (devices slow down at hot temp).
– Device handler input trays and test site are at test temp since
device does not have time to self-heat during short test time.
– Test temp=85C max ambient + (Vcc x Idd active x ThetaJA)
– ThetaJA is package thermal coefficient in oC/W
• Why do performance testing at all since designs are
simulated?
– Simulations are not 100% accurate
• They are models, not reality
• Weather models are only accurate 1 -2 days in advance, since the
entire weather system is too complex to model. Circuit models are
only as accurate as the accuracy of the inputs and the inclusion of
second and third-order effects.
– Manufacturing has variability (Leff, Vt, metalization, etc.)
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Inspect, Mark & Pack
• Inspection
– Devices are inspected by laser inspection equipment for
package and lead coplanarity.
• Devices are marked with Mfg. information
– Lot number, speed grade, manufacturer.
• Devices are mounted for shipping.
– Tape and reel is most common.
• Reels then receive 24 hour bake at 125C and are
sealed in a hermetic bag.
– Plastic mold compound absorbs moisture which, if not
baked out, will vaporize during IR reflow or solder
wave steps of PC board assembly. (“popcorning”)
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Economics of Si Manufacturing
• Profit = Revenue - Expenses
• Revenue = product_price * volume
• Expenses = manufacturing_cost + NRE (eng
costs) + COS (cost of sales).
• Product_price driven by market
– You cannot directly control it
• Product Engineer is responsible for
– Low manufacturing cost / high yield
– High volume manufacturing capability
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Manufacturing Cost and HVM
• Incremental Processing Costs at each step
• Yield losses occur at each step
– Wafers rejected in fabrication line, including
etest
– Dice rejected at wafer sort
– Dice and packaged dice (units) rejected at
assembly
– Units rejected at final test
– Units rejected at inspect, mark & pack.
• Take your yield losses early in the process!
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Mfg. Steps and Typical Costs
• Processed Wafers (8 in) - ~$2000 /wafer
– (Raw wafers ~$100)
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Wafer Sort Assembly Burn-In Class Testing -
$50-$100 /wafer
$0.05-$10 /device
$0.10-$1 /device
$0.10-$5 /device
• Note: These numbers are for instructional purposes only and do not
reflect the costs of any particular product or manufacturer.
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Cost
•Every process step costs money!
•Every process step reduces the number of good
devices!
•The value of any added process step (e.g. another
layer of metal) must outweigh its negative impact on
product cost.
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Assembly Yield Loss
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Initial visual inspection rejects
Die attach problems
Wire bonding problems
Injection molding problems
Package delamination
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Major Sort and Class loss factors
– Point defects
– Predominate at sort
– Parametric yield loss
– Predominates at class
– Gross parametric variation will be caught at
E-test.
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Point Defects
• Characterized by fatal defect density
– Not all defects cause failures
• Affects random die on wafer
• Caused by dust particles and other isolated defects
• Can be modeled with with a Poisson distribution
Y = e(-AD)
where:
Y= yield (1.0 max)
A = area of die D = defects / unit area
• Note: Die area is often expressed in mils. (1mil = 0.001in)
• Yield is exponentially dependent on die area!
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Why die size is critical
• Number of die increases with the decrease of die
size.
• Yield increases exponentially with the decrease of
die size.
• Therefore, smaller die = more die per wafer and a
higher percentage of them being good die.
• Two factors working in the same direction to
produce more good die for the same processing
cost!
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Other Yield Models
• The Poisson Model assumes the defect density is constant
across each wafer and from wafer to wafer. It applies well
to devices with small die size.
• Murphy Model
Y = [(1 - e-(AD)) / (AD)]2
– Assumes that defect density varies and is Gaussian with
the lowest value at the center of the wafer
-(AD)1/2
• Seeds Model
Y=e
– Assumes that the defect density varies and is
“clustered”
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Defect Density
• Calculate defect density for a fab process using area and
yield information from multiple products already being
manufactured.
• Use this defect density to predict the yield of future
products according to their area.
• Defect density can also be used to compare:
– Defect density variation between shifts, pieces of
equipment, fabs, etc.
– Effectiveness of process improvement changes.
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Parametric Yield Loss
• Caused by process shift away from nominal
• Affects entire wafer
• Leff - Effective length of gate
– Changes performance of devices
– Can cause drain-source leakage
– Called Len for n-channel, Lep for p-channel devices
• Vt - Threshold voltage
– Change trip point of devices
– Performance affected
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Parametric Yield Loss (cont.)
• Gate Oxide thickness
– Capacitance changes
– Performance affected
• Metal problems
– Stringers
– thin metal
– Via connectivity
• All parameters are measured with process
monitors.
– In-line monitors and at etest.
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Parametric Yield Loss (cont.)
• Some parametric yield problems still
produce usable parts.
• Parametric shifts that cause performance
degradation can be sold as lower speed parts
(at a lower price).
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Other Economic Considerations
• Capacity - The lowest die costs are achieved when
the expensive mfg. equipment is fully utilized.
– $2M tester, obsolete in 4 years = $500k / year
– 10k units/year = $50/unit, 1M units/year = $0.50/unit
• Die size increases, low yield, long test times, etc.
may result in the inability to make enough parts to
meet the demand with current equipment.
• This may require an additional investment of
millions of dollars, in the case of a tester, or $2
billion, in the case of a fab, to meet the demand.
• e.g. 4sec -> 5sec test time = 25% increase in testers x 40 testers
(@$3M each) = $30M!
• These costs end up raising the price of the product.
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Other cost factors
• The cost of the equipment is not the only
factor which determines processing cost
• Other cost factors:
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Maintenance costs
Consumables (electricity, chemicals, etc.)
Operator labor costs
NRE for developing the tests
Other process-specific costs
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Design for Testability
• Design for Testability (DFT) plays a significant
role in reducing test time and improving test
coverage.
• DFT starts with the definition of the product, since
test modes are part of the design
• Is sometimes called Design for Manufacturability,
although DFM usually refers to device layout
restrictions (bond pad sizes, minimum metal
spacings, etc.).
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Controllability / Observability
• The two main concepts in DFT are:
– Controllability: How easy it is to control (toggle) a
particular node from primary inputs
• Inputs have the highest controllability
• More logic between an input and a node= lower controllability
– Observability: How easy is it to observe the behavior of
a particular node at primary outputs
• Outputs have the highest observability
• More logic between a node and an output= lower observability
• Most DFT modes are implemented to increase
Controllability or Observability.
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Common Test Modes
• Common test modes are
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PLL Bypass / PLL Monitor
All “1”, all “0”, all “Z” modes
Icc standby (Iddq) mode
Electrical ID readout
Process monitor
• The listed test modes are neither required nor
comprehensive.
• Most of these modes will be used only during
device or board test (not end users, not during
normal operation).
– Test modes are similar to “breaking device into smaller
pieces” to test.EEE-287
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Test Mode Logic
• In order to enter test modes, additional
device logic is required
– Often activated by driving a “test#” pin low
– An internal state machine senses this and enters
test mode (exact mode chosen depends on
values on other pins, contents of a control
register, etc.)
– Test logic then “takes control” of the chip and
puts it into desired test mode
• May interfere with device operation, e.g. all tristate
• Or only interfere with a few pins (e.g. PLL monitor)
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Test Mode Logic Diagram
• Simplified test mode logic circuitry:
– Req pins normally input to core logic.
– When test# is low, req
pins select which test
mode is active.
– In case shown, test mode
is disabling (tri-state)
all outputs.
addr0 addr1 addr2
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enabl
e
test logic
test#
JTAG (IEEE 1149)
• JTAG is a standardized test logic interface.
– Stands for “Joint Test Action Group” that developed it.
• Requires 4 pins (TCK (clock), TMS (mode select),
TDI (data in), TDO (data out)
• Allows for versatile test mode implementation
– User can shift in commands and shift data in/out
– Test logic can be used concurrently with normal
function
– Test modes may include a BIST (Built-In Self-Test)
mode.
• Same interface and state machine function for all
devices using this standard
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PLL Bypass / Monitor modes
• PLL Bypass:
– For some tests, we want to have direct control
of a clock normally generated by a PLL (e.g.
slow speed testing, Si debug)
– Insertion of a mux in clock path provides this.
• PLL Monitor:
– PLL monitor mode inserts mux in output paths
of non-critical outputs to bring out the internal
clock and PLL lock signal directly to primary
outputs.
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All 1, 0, Z test modes
• Drives all outputs and bi-directional pin values to
logical 0, 1 or tri-state (pullup/down disabled).
• Used to test Vol, Voh and leakage of buffers.
• These tests could be performed without special
test modes by searching vector patterns for
particular required value on each output.
• This would be engineering intensive and would
greatly increase test time.
• These modes increase controllability
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Icc standby (Iddq) mode
• Used to test current draw of device in lowestpower state possible.
• Tri-states all outputs, disables internal
pullup/pulldown, disables sense amps, PLLs, etc.
• Aberrant current measurements indicate
manufacturing faults (latent functional or timing faults).
• May (or may not) find timing failures or latent
failures not caught by functional tests (resistive shorts)
• This will reduce devices which fail during burnin
or at class (speed) test.
• Excellent test to perform along with functional
tests.
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Process monitor (Procmon)
• Used to determine speed of core transistors
independent of core circuitry.
• Uses numerous inverters in series to amplify effect
of speed changes.
– 30pS speed change for one gate becomes a 3nS speed
change for 100 gates in series.
– Measurement-to-error ratio is improved by 100x
• Often used by third-party ASIC vendors to
“guarantee” speed performance.
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Other DFT modes
• Counter test modes
– Break big counters into multiple small ones
– Run them in parallel
– Bring terminal count pulse to output
• Observation test modes
– Bring out hard to observe signals on output pins
• Direct Access Test (DAT) modes
– Fault grade functional blocks with known good vectors
applied directly to them
– Provide access to local inputs/outputs from device pins.
– Commonly used for embedded memories (RAM)
• Memory testing utilizes extensive unique test methods
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DFT’s Growing Importance
• DFT is growing in importance due to:
– Faster time-to-market requirements
• Leaves less time to develop test vector suites
– Higher quality goals
• Requires more comprehensive testing of devices
– Increased gate count and decreased IO count
• More complex designs continue to reduce
controllability and observability of internal nodes
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Exhaustive Testing
• Test every possible combination of inputs
• For hex inverter, requires 64 vectors (26)
• For 32 bit adder, requires 265 vectors
– At 1GHz = 1170 years!
• For sequential circuits, the problem is worse
(vectors = 2(n+m) where n=inputs, m=flip-flops).
– Clocks not counted since they are not logical inputs
• Grow exponentially worse with device
complexity.
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How do you quantify non-exhaustive
testing?
• Since exhaustive testing is impractical, develop a
vector set that seems comprehensive.
– e.g. For 32 bit adder, add 1000 pairs of 32 bit numbers.
• How can you judge how well these vectors will
find defects?
– How well will it find “dead” transistors, signals shorted
to Vcc or ground or other signals, open connections,
etc?
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Fault Grading
• Fault grading is the process of developing
test vectors and evaluating their
effectiveness in detecting manufacturing
defects.
– A measure of the “goodness” of the vector set
• The “stuck at” (s@) fault model is the most
popular model for evaluating vector sets.
• Most defects can be modeled as a node s@1
or s@0
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Stuck @ detection
• To detect a s@1 fault:
– Propagate a “0” to the fault
location
– Propagate a difference in
local output to primary
output
• A s@0 is detected by
propagating a 1 to the fault
location.
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‘0’
‘1’
‘0’
s-a-1
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‘1’
Fault Grade Process
• Load device netlist into simulator
• Insert (seed) a logic fault in the circuit (short node to power or ground)
• Run logic simulation of vector set on faulty circuit and good circuit in
parallel.
• If any of the primary outputs differ (1 vs. 0) the fault is detected.
• Remove seed from list and rerun with next seed.
• Number of fault detected divided by number seeded is the “fault
grade” for those vectors.
• An 85% fault grade does not mean 15% of real-world defects escape.
– It means that 15% of single-node stuck-at faults would be missed.
– Other tests, such as Iddq, find other type of faults missed by FG.
– A defect is more likely to hit large-area structures like IO buffers.
– True outgoing defect rate must be measured and correlated to FG.
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Drawbacks to Functional Testing
• Compute intensive (>100k faults is common)
• Exponentially diminishing returns with each vector
– May get >50% FG with first vector set
• Doing any basic cycle will use most of devices major functional
blocks (Input buffers, Output buffers, Control logic, Data paths, etc.)
– Second vector set may add 15%
– Third vector set may add 3%
– By 20th vector set , may be adding less than 0.1% per vector
• Methodology “runs out of gas” at 60-80% FG range.
– Large devices may well require over 80% FG to meet DPM goals
– May require person-years of senior engineer time to write targeted
vectors.
• Methodology still requires additional DFT modes
– Counter dividers, RAM direct access testmode, etc.
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Structural Stuck-at Testing
• Does not run device bus cycles
– These have already been done at silicon debug and
system validation testing
• Tests that device was built correctly
– Tests the structure of the device, not the function
• Proves that device is good because:
– Design has previously been proven correct.
– Structural testing demonstrates that all the gates were
made correctly and are connected correctly.
• Most common structural test method is scan
testing
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Scan Test Concept
• Connect all flip-flops into serial chains by
converting each flop into a mux-flop
– Serial “scan” mode selectable by scan enable signal
Synchronous
Design Model
In
D
Q
D
Q
The same design after
scan insertion
D0
D0
D
Q
D1
D
Q
D
Q
D1
Scan Enable
D
Q
D
Q
D0
D0
D
D1
Out
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Q
D1
Scan test methodology
• To Test Sequential Logic (i.e. flip-flops)
• Place device into scan mode, feed unique data into one end of
chain and compare against data coming out
• To Test Combinatorial Logic:
– Place device into scan mode
• Shift data into scan chains to preset entire device
• Drive Primary Inputs to known states
– Place device into normal mode and clock once
• Allows data to flow through combinatorial logic and be
captured in the next flop
– Place device into scan mode.
• Shift data out and compare against known-good results (next set
of data is being shifted in at same time)
– Repeat Unload/Load - Capture - Unload/Load sequence
until desired fault coverage is attained.
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Scan Advantages / Disadvantages
• Advantages of Scan
– Provides very high level of observability/controllability
– Provides high fault coverage (90+ percent achievable)
and burn-in toggle coverage
– Highly automated process
– Facilitates other techniques such as fault isolation
• Disadvantages of Scan
– Costs die size for gates/routing
• Offset by time-to-market, better quality, higher BI yield, etc.
• No extra die size needed if there is unused “whitespace”
– Adds delay to circuit speed paths
– Constraints on usable circuitry during netlist synthesis
– May not find paths that are functional, but slow
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Built-In Self Test
• Built-In Self Test (BIST) adds DFT circuits
and utilizes some of the existing circuits to
test the device.
– For logic devices, scan circuitry, along with
pattern generation and pattern checking circuits
are added to allow the device to test itself.
– For memory circuits, DFT circuitry is added to
cycle through addresses and perform read and
write functions.
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VLSI Processing Overview
• Typical Steps for a CMOS process
• Issues encountered in manufacturing
Simplified Process Overview
• Note:This list is greatly simplified and
omits many critical steps. It is for general
conceptual teaching purposes only.
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Start with P- epitaxial layer (0.3mils) on P+ substrate (30mils)
Nwell and Pwell creation
Field Oxide growth
Gate Oxide Growth
Create PolySi Gates
Create Source/Drain regions
Open Contacts
Create Via1, Metal1, Via2, Metal2, Via3, Metal3, etc.
Create Passivation layer and Open Bond Pads
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Typical Steps for Wafer Processing
• Repetitive Lithographic Process
– Create layer to be patterned (e.g. oxide, metal,
polySi, polyimide)
– Spin on photoresist
• Negative resist hardness in light. Faster, but inferior
line control.
• Positive resist softens in light due to breaking of
polymer bonds.
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Image the structures using a mask and develop
Etch away unwanted material
Clean (and possible planarize)
Repeat for next structure.
2
1
Photoresist
oxide
Si
3
Mask
4
Etch
5
Clean
Typical Steps for Wafer Processing
• Used for:
– Defining diffusion and ion implant areas to add
dopants to Si
– Opening holes in oxide for contact and gate
regions
– Shaping connectivity paths of metal and
polysilicon
• Typical process can require 12-25 masks
Si Cross Section
Processing Techniques
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Oxide Growth
Plasma or Wet Etching
Diffusion
Ion Implantation
CVD - Chemical Vapor Deposition
Evaporation
Sputtering
Planarization
Oxidation
• Uses
– Gate insulation
• Can generate a high quality oxide
• Tends to be a slow process so thickness can be
tightly controlled
– Diffusion mask
– Circuit passivation
• Created by exposing surface to O2 or H2O
and high temperature
– Analogous to rusting of iron
Etch
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Allows selective removal of material
Wet acid etching is isotropic (all directions)
Plasma etching is anisotropic.(vertical wall)
In plasma etching, high energy plasma
sputters material from surface.
• Etches are either timed or evaluated by end
point indicators.
Etch
Wet Etch
Plasma Etch
Diffusion
• One of two ways to introduce dopants in a
controlled way.
• Relies on concentration gradient to induce flux.
• Semiconductor diffusion carried out at 900-1100C
• Typically use Boron to create P type and
Phosphorus or Arsenic to create N type.
• Arsenic diffuses faster than Phosphorus.
• Constant source vs. Limited Source
Diffusion
Diffusion Profile
Ion Implantation
• Second way to introduce dopants in a controlled way
• Ions of the dopant of interest are accelerated in an
electric field
• These ions are then focused on the Si wafer.
• The depth these ions reach is dependent on their
energy and their angle to the lattice.
• 50keV - 1MeV is typical
• Distribution is gaussian with a wider spread for deeper
implants
Ion Implantation
Implant Profile
Ion Implantation
• Advantage
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Highly controlled vs. diffusion
Easily masked
Can form shallow junctions
Doped regions can be buried (low-R regions)
• Problems
– Heavy damage to Silicon
– Highly peaked distribution
– Expensive
• Solution to damage and peaked distribution
– High temperature anneal (also “activates” dopants)
• Can be used for accurate Vt adjust
CVD
• Chemical Vapor Deposition
– Deposits material on top of wafer
• Gas phase reaction: e.g.
– SiH4 (Silane) + O2 -> SiO2 + 2H2
– SiH4 (at 650C) -> Si + 2H2
• Used for polySi (gate) or amorphous SiO2 (ILD)
• Typically does not create single-crystal silicon.
• Creates lower quality oxide than oxidation.
– Not used for gate oxide
Evaporation
• Traditionally used to metalize wafers with
Aluminum
• Aluminum is heated in a vacuum until it
vaporizes.
• It then condenses on the wafer
• Inexpensive process but
– Step coverage can be a problem
– Not a very clean process
– Must break vacuum to change materials
Evaporation
Sputtering
• Uses a high-energy ion to “sputter” material from
a target to the Si substrate.
• Used for substances with high vaporization
temperatures or alloys in which the elements have
greatly different melting points (e.g. TiN or TiW)
• More uniform and cleaner than evap but more
expensive.
• Used for Aluminum for consistency and no need
to break vacuum between materials
– Metal layers are typically a "sandwich” of multiple
materials for better adhesion, anti-reflectiveness, etc.
Sputtering
Planarization
• At a number of points in the manufacturing
process the wafer is ground flat or
“planarized”.
• This creates a flat field for:
– imaging fine structures.
– evenly depositing material (e.g. metal)
Si Cross Section
Issues Classification
• Functionality
– Certain device functions do not work at any
speed.
• Performance
– Certain device functions do not work at rated
speed.
• Reliability
– Functionality or performance of device degrade
over time.
Common Processing Problems
•
•
•
•
•
•
•
Mask Registration
Channel Length Variation
Diffusion Profile (Bloating)
Interconnect (Metal/Poly) Quality
Dopant Concentration
Gate Oxide Thickness
Gate Oxide Quality (crystalline structure)
Registration
• Each Layer is Constructed Using 1 or More Masks
• The “Registration” or Alignment Of Masks For
Different Layers Is Difficult
• A misalignment of <1mm could cause problems
• Can cause functionality, reliability and/or
performance problems.
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Tony Osladil
Example of Registration Error
•
Source: “Atlas of
IC Technologies”
by W. Maly
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Tony Osladil
Channel Length Variation
• Transistor Channel Length is a critical parameter for
performance
• Ldrawn is the polySi gate length drawn at mask design
• Lexposed is the actual polySi gate length manufactured on
the wafer (a.k.a. poly CD)
– Lexposed may be larger or smaller than Ldrawn
• Leff is device channel length after out-diffusion (bloating)
– Leff is always smaller than Lexposed.
• Lelectrical is the channel length after the application of
bias voltage on the transistor and the resultant modulation
of the depletion region
– Lelec is always smaller than Leff
– Lelec “channel modulation” has a greater effects on short-channel
devices
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Tony Osladil
Diffusion Dimension Variation
• Difficult to fabricate exact Widths, Lengths and
Depths of features
• Methods used for introducing dopants leads to
“fuzzy” boundaries
• Further compounded by out-diffusion during
future thermal processing steps (“bloating”)
• Can cause functionality, reliability and/or
performance problems.
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Tony Osladil
Example of Bloating
gate
Bloating of drain
under gate
Photos from the Textbook “Atlas of IC Technologies” by W. Maly
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Tony Osladil
Interconnect Quality
• Variations in metal width and thickness
cause variations in resistance.
• Metal/Via/Metal connection problems
increase resistance.
• Variations in inter-layer dielectric cause
variations in capacitance.
• Topological considerations
– Stringers
– Step Coverage
Topological Considerations
• Different Layers Of Material Placed Upon
Each Other
• Each Layer Adds Topological Features
– Bumps
– Valleys
• Difficult To Maintain Constant Thickness
• Can cause functionality, reliability and/or
performance problems.
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Tony Osladil
Topological Example
Too Thin
Too Thick
ILD
Metal2
Metal1
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Tony Osladil
Stringers
• Conformal coating over vertical feature creates
extra thick coating.
• Etching to remove nominal thickness may leave
material on these vertical walls.
• This creates shorts between metal or poly lines
that route over these vertical features.
• Shorts can be low or high resistance.
• Solutions:
– Tune etch for each design
– Improve consistency of coating thickness
– Planarize each level
Stringer Drawing
Metal2
ILD
Metal2
Metal1
Stringer
ILD
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Tony Osladil
Dopant Concentration
• Variations cause:
– Shifts in Vt
– Shifts in sheet rho (resistivity)
Gate Oxide Thickness / Quality
• Thickness
– Typical value ~200A (i.e. 200 x10-10 meters)
– Variation can cause shifts in Vt
• Quality
– Interface charges
• “Dangling” bonds
– Trapped charges
– Affect Vt and/or produce leaky, deteriorating
gate junctions
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Tony Osladil
CMOS Function and
Performance
•
•
•
•
•
Review of MOSFET behavior
VT
CMOS performance
Electromigration
Hot Electrons
VGS
VDS
Substrate
Inversion Layer
Gate
Drain
Source
N
P
N
Depletion Region
Threshold Voltage (VT)
• The gate voltage at which strong inversion
takes place.
• When VGS exceeds VT, significant current
flows.
• VT is a function of:
– Insulation thickness
– Channel Doping
– Gate insulation material
Threshold Voltage
• It is important for VT to be the proper value.
• If it is too small, noise will cause device to
start conducting incorrectly and higher
leakage will result.
• If it is too large, the device will not start
conducting until the input signal is a higher
voltage and will delay the output from the
gate.
Threshold Voltage
kT  N A  t ox 2 si qN A 2 b
 
Vt  2
ln
 V fb
q  Ni 
 ox
• Function Of:
– Gate Capacitance
– Doping Concentrations
C OX 
– May be modified with Ion Implantation
– Temperature
 ox
t ox
CMOS Performance
• CMOS switching speed dependent on
– Drive capability of device
– Characteristics of load
• CMOS loads typically capacitive with series
resistance.
• Capacitance comes from interconnect and
from gates of succeeding devices.
• Resistance comes from interconnect R
• Drive capability comes from Rds(on) and
Id(sat) of transistors
DC Performance
2
m ox  W  
Vds

Ids 
  Vgs  Vt Vds 

t ox  L  
2 
• For Given Voltages
• As W Increases Ids Increases
• As L Decreases Ids Increases
• Varies with Vt and somewhat with Vds
•Thinner tox increases Ids
•Affected by mobility
• Electrons have higher mobility than holes
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Tony Osladil
Resistance of a Material
• All Materials Used In CMOS Fabrication
Have A Resistive Impedance
• The Amount of Resistance Depends On:
– The Type Of Material
– The Shape Of The Material
– The Temperature Of The Material
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Tony Osladil
Resistance Estimation
Current
w
   l 
R    
 t  w 
l
t
 = Resistivity, a constant of given material
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Tony Osladil
Equivalence of Resistance
w
l
4w
=
t
4l
t
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Tony Osladil
Resistance Per Square
• Thickness of given material is defined when
the process is defined
• Resistivity of each material is known
• Therefore L and W are the only variables
• Resistance quoted in W/Sq
• Material can therefore be measured in
“Squares”
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Tony Osladil
Example Of Resistance
Calculation
• Poly Silicon: 20 W/Sq
W=10 mm
L = 50 mm
• There are (50/10) = 5 Squares Of Poly
• R = 20(5) = 100 W
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Tony Osladil
Typical Resistance of Common
Layers
•
•
•
•
•
•
Poly
Metal1
Metal2
Metal3
N and P Diff
N-Well and Substrate
20 W/Sq
.07
.07
.04
25
2000
– Resistors can be made from any of these components
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Tony Osladil
Decreasing Sizes Mean Higher
Resistance
• As transistor sizes shrink:
– Widths of metal interconnect decrease
• in proportion with transistor sizes
– Metal thickness decreases
• to allow for complete etch without stringers
• As devices get more complex with more
transistors, average length of metal traces
increases
• Average interconnect resistance increasing
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Tony Osladil
Channel Resistance
0 < Vds < Vgs-Vt
+
VGS
-
N+
N+
Channel
L
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Tony Osladil
Estimating Channel Resistance
• Channel resistance can be estimated by
resistivity times #of squares.
L
Rc  k  
Channel Resistance
W 
Resistivity of Channel
1
k
Depth Of Channel
mC ox (V gs  Vt )
C ox 
 ox
Oxide Capacitance per area
t ox
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Tony Osladil
Resistance In Vias
• Vias have smaller dimensions than minimum
metal, therefore minimum size vias have higher
resistance than a minimum metal wire
• To compensate, multiple vias may be used.
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Tony Osladil
Capacitance Per Area
• Capacitance of Material To Substrate Can
Be Estimated By:
A ox
C
t fox
• Very Rough Estimate
• Does Not Include “Fringing Effects”
• Actual Capacitance Is Slightly Higher
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Tony Osladil
Typical Capacitances Over Field Oxide
• Layer
Metal1
Metal2
Metal3
Poly
attoF/mm2 (aF = 1x10-18)
30
20
10
50
(C between layers is not accounted for here)
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Tony Osladil
Drain and Source Capacitances
C g  C gb  C gs  C gd
Cgd
Cgb Cgs
Drain
Source
Cdb
Csb
Depletion Region
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Tony Osladil
Total Gate Capacitance
• Total Capacitance Is Sum Of All
Components of Capacitance
• Cgb tends to dominate
• Remember: Cg will depend on operating
region FET is in
C g  C gb  C gs  C gd
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Tony Osladil
Electromigration
• When high density current flows through
metal interconnect, the electrons collide
with the metal atoms.
• These collisions can cause the metal to
migrate and eventually create an open
circuit.
• This typically happens at imperfections or
discontinuities in the metal where current
density is the highest.
Electromigration
Hot Electrons
• With large enough electric fields, electrons
become “hot” (high kinetic energy).
• Hot electrons impact the drain and dislodge holes
that show up as substrate current.
– This is called “impact ionization”
• In addition, electrons can penetrate the gate.
– This can cause a Vt shift (reliability problem)
• Problem gets worse with shorter gate lengths
– Same Vcc over shorter distance = higher field strength
– One reason for lower Vcc w/ smaller transistors
– Dopant profiles can be modified to reduce field
gradient
Device Scaling
• Device scaling (shrinking) is a complex process
– IDSat, Vt, Resistance and Capacitance are all changing
– Some effects improve performance, some degrade it.
• Shorter Leff reduces Rds(on), increasing IDSat
– Same resistivity, shorter length = higher I until pinchoff
– Also requires less die size per transistor
• Lower C on gate capacitance of loads
• Lower C, higher R on shorter, but thinner metal
interconnect
– Balances out somewhat, but tends to increase RC
• Metal line loads becoming higher % of total load
– Problem if simulators do not model interconnect loads well
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Tony Osladil
Device scaling (cont.)
• Dopant concentrations change Vt and Rdson
– May be done to reduce hot e- effects
• Vcc may need to be reduced
– Reduced Vcc reduces power density and field strength.
• Lower Vcc decreases power exponentially (P = C * Vdd2 * freq)
• Lower Vcc decreases hot e- effects.
– Lower Vcc also avoids punch-through, decreases subthreshold leakage.
– Vcc reduction will affect performance
• Lower Vcc decreases Idsat and requires Vt reduction
• Vt reduction may require Tox reduction, increasing Cgate
• Not all features scale
– e.g. Vias may not be able to shrink and still etch cleanly
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Tony Osladil
Why is Leff the dominant parameter
in process descriptions?
• Leff is the smallest dimension
– i.e. Most difficult to manufacture accurately
– Can not scale other structures w/o scaling Leff
• Smaller Leff provides better performance
– Increases IDsat
– Decreases Cgate
• Smaller transistors = smaller die= more die per
wafer and better yield percentage
• Reduced Leff produces more good die on each
wafer with better performance!
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Tony Osladil
Parametric Performance
• Devices are designed to meet all performance
criteria.
• Actual Performance may be reduced by global
(e.g. Leff) or point defect (e.g. metal particle)
effects.
– Reduced performance due to global effects depends on
gaussian distribution of critical dimensions.
– Reduced performance due to point defects depends on
random distribution of faults which produce leakage
currents, increased resistance / capacitance or reduced
Idsat.
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Tony Osladil
Leff, Voltage, Temperature Effects
• Device performance depends on moving charge
(electrons) in and out of load capacitance.
– Larger Leff = Lower Idsat = slower switching
– Lower Vcc = Lower Idsat = slower switching
– Higher temperature= Lower Idsat = slower switching
• Slowest = high Leff, low Vcc, high temperature
• Fastest = low Leff, high Vcc, low temperature
• Devices must be simulated and tested at both
worst case conditions
– Slow-corner testing is why overclocking sometimes
works
– “Too fast” can be a problem (see hold time foil)
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Tony Osladil
Parametric Performance Analysis
• Overall device performance often falls into two
categories:
– Maximum clock frequency (Fmax)
– IO timing performance
• Both are based on Setup / Hold / Output_Valid
– Setup Time = The amount of time a value must be present and
stable at an input before the clock transition
– Hold Time = The amount of time a value must remain present and
stable at an input after the clock transition.
– Output_Valid (a.k.a. Tco) is the amount of time from a clock edge
until the output value changes. It moves with Vcc, temp, Leff.
• Max Valid Time = The amount of time until the output of a device has
achieved its new value after the clock transition
• Min Valid Time = The amount of time that an output will retain its
previous value after the clock transition.
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Tony Osladil
Setup / Hold / Min& Max Valid
(Variation over Vcc and temperature)
•
O1
Clk
In
Tsu
Th
O2
O1
In
O3
O2
O3
O4
O4
MinV
MaxValid
Clk
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Tony Osladil
Source of Specifications
• The industry-standard PCI bus has the
following specifications:
–
–
–
–
–
–
–
Tcycle (min) = 30nS (i.e. 33MHz Fmax)
Tsetup = 7nS
Thold = 0nS
TmaxV = 11nS
TminV = 2ns
Tprop(max) = 10nS
Tclkskew(max) = 2nS
• Why?
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Tony Osladil
PCI Bus Timing
1
D1 Q1
0
D2 Q2
Clk(external)
Clk(ext)
Clk1
Clk2
Skew
D1
Q1
D2
MaxV
Tprop
Tsu
Q2
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Tony Osladil
0
Source of Specifications (cont.)
• Setup Time Equation:
• Tcycle > Tskew + TmaxV + Tprop + Tsu
– Tprop may include delay through combinatorial logic
– Tprop on PC board traces ~ 5” / nS.
• Fmax = 1 / Tcycle for all paths
– e.g. 30nS Tcycle = 33MHz max frequency
– Most circuits will have multiple paths using same clock
– If one path Tcycle = 30nS, another path Tcycle = 28nS
and a third path Tcycle = 31nS, Fmax will be less than
33Mhz.
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Tony Osladil
Source of Specifications (cont.)
• What is Min Valid Time for?
– Provides hold time to the next input
• Hold Time Equation:
– TminV+Tprop > Tclkskew+Thold for proper operation
• Tprop may be very close to 0nS (worst case)
• Thold is often 0nS or possibly negative!
– Note that clock skew makes both setup and hold time
equations more difficult to satisfy.
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Tony Osladil
0
1
MinV - Hold Time
D1 Q1 D2 Q2
0
1
1
Tclockskew = 2nS
Tprop = 0.1nS
Thold = 0nS
Clk
Clk1
Clk1
Clk2
Clk2
D1
D1
Q1
D2
TminV=4ns
Thold for “0”
Q2
Q1
TminV=1nS
D2
Q2
4nS min valid produces hold time
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1nS min valid violates D2 hold time
Tony Osladil
Setup and Hold Must be Met!
• Device Setup and Hold times must be met
for reliable operation!!!
• Insufficient setup or hold time produce metastability
• Delayed maxV time, oscillatory outputs and/or wrong output
• Min Vcc, Hot is worst case for meeting setup
– Setup times get worse
– Max Output Valid times get worse (longer)
– Tprop through combinatorial logic gets worse (longer)
• Max Vcc, Cold is worst case for meeting hold
– Hold times get worse
– Min Output Valid times get worse (shorter)
– Tprop through combinatorial logic gets worse (shorter)
• Both scenarios must be simulated / tested
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Tony Osladil
DC Parametric Specs
• Icc standby - Supply Current draw of device in one or
more low-power states (e.g. suspend).
• Icc active - Supply Current draw of device while running
its most compute intensive bus cycles.
• IO leakage - Current that leaks out of inputs / outputs
when pin is in tristate condition.
• Vol / Voh - Output low / high voltage when the output is
sinking / sourcing specified current
• Vil / Vih - Voltage required for input to recognize value
as a logical one or zero.
• Can all fail due to point defects or global effects,
point defects will usually get worse over time.
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Tony Osladil
Input / Output Voltage
• Vil is maximum voltage guaranteed to be recognized as 0
• Vol is maximum voltage outputs are allowed to drive and
still be seen as a “0” (uA or mA output current also spec’d)
• Vih is minimum voltage guaranteed to be recognized as 1
• Voh is minimum voltage outputs are allowed to drive and
still be seen as a “1” (uA or mA output current also spec’d)
• Values are not the same to allow for noise.
Vcc
3.3V or 5V
Voh
Vih
2.4V
2.0V
Vil
Vol
0.8V
0.4V
Gnd
0V
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Tony Osladil
Vix/Vox values are
industry-standard TTLcompatible voltages
for 3.3V or 5V
High-Volume Production Test
• Production test is used to eliminate:
– Functional failures (Correct 1s and 0s go in and out)
– Parametric failures (AC and DC specifications)
– Some latent failures (e.g. aberrant input leakage)
• It is not used to validate design correctness.
– System validation confirmed the design’s correctness.
– Test validates that each part works the same as a known-good
device.
• Production test makes go / no-go decision.
– Uses hardware comparators to determine if an output is
at the correct voltage level at the time it is sampled
– No indication of margin to spec.
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Tony Osladil
Typical Test Program Flow
• Opens / Shorts (pull pin negative, check for diode drop)
• Basic Functional testing (slow clock, loose IO timings and
loose DC values).
• Fault Grade vector testing (same conditions as above, may
be scan vectors or large set of functional vectors)
• Full Frequency Function (clock at full speed, all else loose)
• AC testing (tight IO timings, Vil/Vih/Vol/Voh loose)
• Vil / Vih testing (tight input voltage, all else loose)
• Vol / Voh testing (tight output voltage, all else loose)
• Icc dynamic testing
• Icc standby / Iddq testing
• I/O leakage testing
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Tony Osladil
Combining Tests
• Some tests in the flow may be combined
– e.g. Functionality testing at full frequency with tight
AC and tight Vil/Vih
– Saves test time
• There are some down sides to combining tests
– Some tests won’t run at full speed (e.g. DAT modes)
– Low yield analysis becomes very difficult
• How many parts failed for each type of test?
– Tests may interact negatively with each other
• e.g. High Iol/Ioh may cause ground bounce which
conflicts with tight AC strobing
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Tony Osladil
Typical Tester Architecture
• See other handout
– Overall tester architecture
– Vector memory contains:
• Data, Drive (yes/no), Timing, Format, mask!
– e.g. 1_1_10010110_10_1
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DC current spec testing
• DC current specs are tested with A/D
converters in power supplies or PEC
– Icc active tested during pattern execution
– Icc standby / Iddq tested after a pattern is run to place
device in suspend or Iddq mode
– IO leakage tested after a pattern is run to place device
in “All Z” mode.
• Proper selection of current clamp / measurement
range is important
– Lower current range = more accurate measurement
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Tony Osladil
Current Measurement Ranges
• Current measurements are mode by
measuring IR drop across series resistor
– Resistor value is programmable
– Higher resistance value = more resolution
– Too high resistance overanges the voltmeter
10 ohm = 100mA max I, 100uA resolution
100ohm = 10mA max I, 10uA resolution
1k ohm = 1mA max I, 1uA resolution
5V
A to D
(1Vmax)
Vcc
(DUT)
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A to D converter (voltmeter) is 10 bit (i.e. 1024 steps)
0V = 0000000000, 1V=1111111111
Tony Osladil
Resolution vs. Accuracy
• Resolution is the value of the Least Significant Bit
of your measurement device (granularity)
– +/-1 pound from typical bathroom scale, +/-1 sec from wristwatch
– Determined by number of bits or indicator marks
• Accuracy is how close the measured value is to
the actual value
– Varies by manufacturer of measurement equipment
– Determined by quality of components and design
• Resolution typically cheaper than Accuracy
– 8 -> 10 bit converter improves resolution
– Accuracy requires precision R’s, precision AtoD converters, etc.
• Resolution should be finer than accuracy
– +/-10mA resolution on +/-1mA accuracy meter wastes accuracy
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Tony Osladil
Pin Electronics Cards
• See other foil for Pin Electronic Card (PEC)
architecture.
• Fail = strobe AND data mismatch AND not
masked.
– Fail signal tells tester to stop any further testing
and send signal to handler to put device into fail
bin/tray.
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Tony Osladil
Tester Programmable Loads
• Tester loads are usually programmable
– Iol
– Ioh
– Vfloat
Vcc
Iol
P-channel
DUT pin
V
Vfloat
N-channel
Ioh
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Tony Osladil
Vector tests
• Device functionality and speed are tested by
applying vectors (0’s and 1’s) to the device
inputs and outputs
• Inputs are driven by the PECs
• Outputs are compared at the PECs
– Outputs are compared when PECs are strobed
– If outputs are “masked”, strobes are ignored
Clk (in)
D (in)
Logical “1” on Q is compared against value in
vector memory only when strobe signal is pulsed
Q (out)
PEC Strobe
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Tony Osladil
Functional / Parametric Testing
• Same vectors with different PEC parameters are used to
perform functional and parametric testing.
0nS
3.3V
Functional Test
100nS
0nS
3.3V
Parametric Test
Pass
1.5Voh
1.5Voh
1.4Vol
1.4Vol
Strobe Point
(95nS)
Fail (TmaxV)
Fail
(30nS)
0V
0V
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Tony Osladil
100nS
Functional/Parametric Test (cont)
• Similar method is used for testing Vol/Voh/Vil/Vih
0nS
3.3V
Functional Test
100nS
0nS
3.3V
Pass
Parametric Test
2.4Voh
1.5Voh
Fail (Voh)
1.4Vol
Strobe Point
Fail
0.4Vol
0V
0V
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Tony Osladil
100nS
Tester Drive Formats
• RZ: Return to Zero
– Drives a zero, drives data,
returns to zero
– Typically used for clocks
1
0
R1: Return to One
– Drives a one, drives data,
returns to one
– Typically used for negative
pulses or clocks
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Tony Osladil
0
Tester Drive Formats (cont.)
• NRZ: Non-Return to Zero
– Drives to data value at
specified edge time
– Typically used for data pins
1
0
• SBC: Surround By
Complement
– Drives data!, then data, then
data!
– Typically used for driving data
pins to tight setup/hold specs
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Tony Osladil
1
0
Test Vector Source
• Vectors captured from simulation are run on
devices
– Binary value of a pin will be sampled every “x”nS and
be stored in a table Example: 0101
1110
0010
1010
– Problem:
•
•
•
•
What function does the above values describe?
Could you draw a timing diagram?
The tester has the same problem
Vectors require data, timing and format
– Format is drive (NRZ, RZ, etc.), compare or don’t care (mask)
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Tony Osladil
Test Vector Conversion
• Instead of just 0 or 1 for all drive/compare values, define a
unique character for each:
– Example
•
•
•
•
0 = drive 0 NRZ, 1 =drive 1 NRZ (i.e. data pins)
C = drive 1 RZ, c = drive 0 RZ (i.e. clock pins)
L = strobe 0, H = strobe 1 (i.e. output pins)
a=drive@1nS; b=drive@10, 20 nS; c=strobe@30nS
• Vector Conversion software tools use if-then rules to
substitute these characters for simple 0 or 1
• Example: If column4 = 1, replace with H, else replace with L
• If column3 = 1, replace with H, else replace with L
• Produces 0101 => 01LH
– After converting all columns and adding timing
information for each pin, 0101 becomes 0CLH, abcc
• 0CLH, abcc now contains data, format and timing
information for each pin
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Tony Osladil
Converted Vectors
0101
1110
0010
1010
0CLH, abcc
1CHL, abcc
0cHL, abcc
1cHL, abcc
• Vectors listed above drawn as timing diagram below
0nS
40nS
80nS
120nS
D
Clk
Q
Q!
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Tony Osladil
160nS
What do you have to tell a tester?
• Test Order
– Open/Short, Basic func, Iddq, etc.
• Content of each test
–
–
–
–
DC levels (Vcc, Vil/Vih, Vol/Voh, Iol/Ioh)
Timings (i.e. Where are the edges?)
Which pattern(s) to run
What voltage or current measurements to make
• Pass/Fail “Bin” for each test
– Multiple pass bins used to segregate by performance
– Multiple fail bins used to analyze failure pareto
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Tester Code Development
•
•
•
•
•
Flow and Bin file
Test content file
Levels definition file
Timing definition file
Pattern definition
file
TIMING FILE
PATTERN FILE
all_patterns:
*read_from_PCI
*write_to_PCI
*read_from_USB
*write_to_USB
read_patterns:
*read_from_PCI
*read_from_USB
loose_timing:
*input=1nS
*clock=30nS,80nS
*strobe=90nS
*tcycle=100nS
FLOW AND BIN FILE
Opens
Shorts
Basic function
Tmaxvalid test
Tminvalid test
Icc dynamic
If no fails
LEVEL FILE
loose_levels:
*Vil=0V
*Vih=3V
*Vol=1.4V
*Voh=1.6V
*Vcc=3.3V
maxv_timing:
*input=25nS
*clock=30nS,80nS
*strobe=36nS
*tcycle=100nS
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bin10
bin11
bin12
bin13
bin 14
bin 15
bin1
CONTENT FILE
Basic function:
*loose_levels
*loose timing
*all_patterns
Tmaxvalid test:
*loose levels
*maxv_timing
*read_patterns
Device-specific test hardware
• Probecard for wafer sort
– PC board with a hole in the middle
– Connects PECs to needles which land on bond pads
• Loadboard for packaged device final test
– PC board with a socket / contactor on top
– Connects PECs to socket pins
• Probecard/Loadboard may have passive or active
circuitry
– Passive: Bypass caps, impedance matching resistors
– Active: Relays, voltage regulators, etc.
– Components must be verifiable as functioning correctly
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Transmission lines
• A large problem with test hardware is transmission
line effects
– Causes “steps” in the waveforms
– Causes overshoot of Vol / Voh
• If the risetime of a signal is shorter than the travel time
down a wire, then the far end of the wire does not “know”
what value the near end is at, and the near end does not
“know” how the far end is terminated.
• Basic idea is that as a current wave travels from a driver,
through a trace and arrives at a load, it encounters different
impedances (R + (LC)1/2), producing different voltages.
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Transmission line waveforms
•
Z(driver) = 50ohm
Z(trace) = 50ohm
R(termination) = 1M
Z(driver) = 10ohm
Z(trace) = 50ohm
R(term) = 1M
3.3V
3.3V
Tprop Tprop
Reflected wave
Incident wave
0V
0V
“Step” voltage = Vcc x 50 / (50+50) = 1.65V
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“Step” voltage = Vcc x 50 / (10+50) = 2.75V
Tony Osladil
Transmission line solutions
• Utilize the tester’s programmable load to
change the impedance of the termination
• For low-impedance outputs, add series
resistors to match the trace impedance
• For high-impedance outputs, move your Vol
and Voh levels to check for the rise/fall time
of the incident wave.
– Remember that wave doubles when hitting receiver
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Tony Osladil
Loadboard/Probecard Calibration
• Trace lengths on loadboards / probecards produce
timings delays which corrupt tester accuracy.
• Each trace must be balanced
– Drawn with equal lengths (still has round-trip delay)
OR
– All channels measured and small delay is added to
faster channels
– Tprop is subtracted from drive edge and compare time
• Transmission line reflections are used to measure
delay of each trace.
– Must be performed each time new loadboard mounted.
• Often called “focus calibration”
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Tony Osladil
Capacitive Derating
• Tester/loadboard capacitance affects output timings
– Lumped C at receiver degrades risetime, increases max valid time
– 0% to 50% risetime is 0.7 RC time constant
– RC time constant of load is lumped C and the Z of transmission
line (or the Rds_on of the driver if not a transmission line)
• Output timing specs are based on specified load C
– Sometimes 0pF!
• Tester results must be correlated to spec’d capacitance
– Correlation factor can come from simulation or from empirical
measured data.
– Correlation will have some amount of error.
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Guardbanding
• Even after calibration, all measurements have error.
• Testers have specified Edge Placement Accuracy (EPA)
– Typical range of +/-100pS to 1000pS per edge.
• Overall Tester Accuracy (OTA) = 2x EPA
– e.g. Input edge early, clock edge late
• OTA must be subtracted from a max spec value (or added
to a min spec value) to guarantee no failing devices are
passed
– The guardbanded limit must make it more difficult for
the part to pass the test.
– e.g. 7nS setup time, 250pS tester EPA = 6.5nS test limit
• Designs must target these reduced specs
• As values of specs (and margins to spec) get smaller,
guardband has greater impact on yields.
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More Guardbanding
• Other test equipment also has error
– Voltage supplies
– Current supplies (e.g. Iol / Ioh)
– Temperature control systems
• To completely guarantee spec compliance, all
must be guardbanded!
– e.g.
3.0V Vcc min actually set at 2.9V
• Guardbanding each force/measure parameter is overkill,
but where do you not guardband and still guarantee spec?
• Some manufacturers “reverse” guardband to
guarantee no good units are failed.
– Will produce devices that do not meet worst-case specs.
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Parametric Characterization
• Although testers are pass / fail in production, They
can be used for characterization (datalogging).
– Icc / Iddq measurements:
• Current values are read from A/D converters
– AC timing measurements:
• Run vector file(s), move strobe, re-run vector
• Repeat until pass/fail boundary is found.
– Vil / Vih / Vol / Voh measurements:
• Uses same repetitive search technique
• Vix / Vox value is changed at PEC card
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Linear / Binary Searches
• To provide +/- X picosecond resolution:
– Linear Search:
• Start at max possible value, run vector(s)
• Move strobe XpS earlier in the cycle, rerun vector(s)
• Repeat until pass / fail boundary is found
– Binary Search (aka Successive Approximation):
• Start at max possible value, run vector(s)
• Move strobe to center of search range, rerun vector
• If fail, define new search range as upper half of old search
range
• If pass, define new search range as lower half of old search
range
• Repeat until new search range is equal to X picoseconds
• Why called binary?
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Linear / Binary Search Tradeoffs
• Linear Searches
– Max number of search steps, n = Search Range / resolution
• e.g. 100nS search range, 50pS resolution desired, n < 2000
– Slower than binary searches.
• Binary Searches
– Max number of steps = n, where 2n = Search_Range/resolution
• e.g. 100nS search range, 50pS resolution desired, n = 11
– Faster than linear searches
• Doubling resolution or search range adds one step
– Not reliable for finding multiple or changing values
• e.g. Inputs with hysteresis
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Tester Debug Tools
• During device or program debug, more
information is needed than pass / fail.
– Datalogger - Displays DC readings and/or failed
vector number.
– Breakpoint - Allows user to stop program execution
at any point to analyze/modify test results/conditions
– Waveform Display - Displays selected pin
waveforms over selected time (vector number) range.
– Interactive Control - Allows modification of
voltages, currents and timings w/o program re-compile
– Shmoo Plot - Allows graphical pass / fail display of
two parameters varied against each other.
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Shmoo plot example
• Shmoo plot of device
with two Vdd pins
driven by two power
supplies (PS1 and PS2).
• Shows that device
works at Vdd(min)
(i.e. 3.1V) on Vdd1 or
Vdd2 but not both
simultaneously.
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Quality and Reliability
• Quality
– Does it meet all requirements now?
• Reliability
– Will it meet all requirements over the usable
life of the product?
• Q&R need to be built in, not tested in.
– Some reliability defects not detectable without
destructive testing (e.g. bond wire integrity).
– May be able to screen Q&R failures, but at high cost.
• High cost of test (e.g. X-ray each device)
• High cost of scrap (after much added-value work)
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Q&R Cost Implications
• There is cost/Q&R tradeoff between extremes of:
– Poor materials, poor manufacturing and no testing
– Ultra-pure materials, controlled high-quality
manufacturing and exhaustive testing
• Cost / Q&R balance depends on user requirements
• High Q&R is required for applications with:
–
–
–
–
High rework costs (e.g. Hubble telescope)
High volumes (e.g. Sony Walkman)
Long lifespan (e.g. communication satellites)
Life or livelihood dependence (e.g. pacemakers,
corporate mainframe)
– Contractual requirements (e.g. military specifications)
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Q&R Cost (cont.)
• Low Q&R is sometimes acceptable
– Where cost is crucial
– Rework costs and life span not important
– Examples: student projects, “talking” greeting cards
• Moderate tradeoffs are used in industry
–
–
–
–
Not all devices receive Burn-in
Devices are not always tested at full speed
Produces higher customer and end-user failure rate
Most often associated with ASIC manufacturing
• ASICs are made by wafer foundry companies for fabless chipdesign companies
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Semiconductor Q&R
• High Q&R is critical to the long-term
success of major semiconductor companies.
• Multi-stage inspections are done:
– Incoming materials inspection
– In-line metrology
• e.g. metal line-width measurements, bond pull tests
– Qualification testing of new processes, device
or packages
– Production screen of each component (BI, test)
– Ongoing reliability monitors
• Qualification tests re-done on ongoing sample basis
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Qualification testing
• Qualification testing is done to prove the
reliability of new processes, devices or packages.
• Qual testing will be done on a representative
sample the first few production lots, not every lot.
– Infant Mortality Evaluation
• Finds Infant Mortality Levels and BI time required
• 125C, max Vcc, high node toggle coverage, 168 hrs
• Failure rate measured in DPM (Defects Per Million
devices)
• Typical targets < 1000DPM
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Qualification Testing (cont.)
• Extended Life Test
•
•
•
•
•
Determines reliability over lifespan of product
125C, max Vcc, high node toggle, 1000 hours
Failure rate measured in FIT (Failures In Time)
Failures In Time = Failures per 109 device hours
Typical target < 500FIT,
– 2 failures out of a sample of 250 devices over 2000 hours
of burnin with an acceleration factor of 200 = 20FIT.
– This equates to 1 million units in use in the field for 1000
hours producing 20 failures.
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Qualification testing (cont.)
– Steam
• Tests moisture resistance and passivation integrity
• 121C @ 15PSI, 168 hours, no electrical bias
– Temperature / Humidity / Bias (85/85)
• Tests moisture resistance with bias applied
• 85C, 85% R.H., Vcc applied, min Icc, 1000 hours
– Temperature cycle
• Detects mechanical reliability and thin-film cracking
• -65C to 150C, 1000 cycles, no electrical bias
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Qualification testing (cont.)
• Device/Package Qualification tests (cont.)
– Electrostatic Discharge (ESD)
• Tests ability to withstand static discharges
• Each pin zapped at 2kV, 100pF, 1.5k ohm (Human
Body Model)
• Each pin zapped at 1kV, 100pF, 0 ohm (Charged
Device Model)
– Latchup
• Tests immunity to SCR latchup
• Vcc raised to above Vccmax, Icc measured.
• Current forced in and out of IO pins, Icc measured
– Other tests are possible (e.g. vibration)
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Tony Osladil