Transcript POWER Everywhere Announcement Training - Part2

Power Everywhere
POWER5 Processor Update
Mark Papermaster
VP, Technology Development
IBM Systems and
Technology Group
© 2004 IBM Corporation
POWER : The Most Scaleable Architecture
PPC 750
PPC 603e
POWER4
PPC 750FX
PPC 750CXe
POWER5
PPC 970FX
PPC 750GX
PPC 440GX
Binary Compatibility
POWER2
POWER3
POWER4+
PPC 440GP
PPC 405GP
PPC 401
© 2004 IBM Corporation
IBM Powers Mars Exploration
►
PowerPC is at the heart of the BAE Systems RAD6000 Single Board
Computer, a specialized system enabling the Mars Rovers — Spirit and
Opportunity — to explore, examine and photograph the surface of Mars.
► In fact, a new generation of PowerPC based space computers is ready
for the next trip to another planet. The RAD750, also built by BAE
Systems, is powered by a licensed radiation-hardened PowerPC 750
microprocessor that will power space exploration and Department of
Defense applications in the years to come.
© 2004 IBM Corporation
POWER4 Recognition --- January 2002
“… considering system scalability,
bandwidth, chip-level
multiprocessing, fault tolerance,
and performance --- it is
impossible to ignore the
accomplishments of the IBM
POWER4 architecture …
“It has … actually met shipment
schedules publicized 2 years ago;
and generally lived up to the
promise.”
– Kevin Krewell
Senior Analyst, Microprocessor Report
© 2004 IBM Corporation
POWER4: Foundation for Systems Value
POWER4
First dual-core microprocessor
High-end
Mid-range,
Low-end
© 2004 IBM Corporation
POWER Server Roadmap
2001-2
2002-3
2004-5
2005-6
2006-7
POWER4
POWER4+
POWER5
POWER5+
POWER6
90 nm
65 nm
180 nm
1.0-1.3
GHz Core
1.0-1.3
GHz Core
130 nm
1.2-1.9
1.2-1.9
GHz Core GHz Core
Shared L2
Shared L2
Distributed Switch
Distributed Switch
Chip Multi Processing
- Distributed Switch
- Shared L2
Dynamic LPARs (16)
Reduced size
Lower power
Larger L2
More LPARs (32)
130 nm
> GHz
Core
> GHz
Core
Shared L2
>> GHz >> GHz
Core
Core
Ultra high
frequency cores
L2 caches
Shared L2
Distributed Switch
Advanced
System Features
Distributed Switch
Simultaneous multi-threading
Sub-processor partitioning
Dynamic firmware updates
Enhanced scalability, parallelism
High throughput performance
Enhanced memory subsystem
Autonomic Computing Enhancements
© 2004 IBM Corporation
POWER5™ Objectives
Build on POWER4 base
► Maintain binary and structural compatibility
► Enhance and extend multiprocessor scalability
► Continue superior performance
► Provide breakthrough virtualization server flexibility
► Deliver power efficient design
► Enhance reliability, availability, serviceability attributes
© 2004 IBM Corporation
POWER5 Systems --- A New Standard
►
Second generation dual
core chip
► Intelligent 2-way SMT
► Power management with no
performance impact
► 130 nm lithography
 276M transistors
 8 layers of metal
►
Eight way SMP looks like 16-way to
software
► All that’s needed is DIMMs and I/O
► 95 mm on a side
► Performance equivalent
to >4 p690 MCMs
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►
Micropartitioning
► Up to 64 physical
processors,1280 virtual
processors per system
► Virtual I/O
► Virtual LAN
© 2004 IBM Corporation
Modifications to POWER4 to
create POWER5
P
P
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L2
P
Reduced
L3
Latency
L2
Larger
SMPs
Fab Ctl
Fab Ctl
L3
Cntrl
L3
Mem Ctl
Memory
L3
Cntrl
Faster
access to
memory
Number of
chips cut
in half
L3
Mem Ctl
Memory
© 2004 IBM Corporation
Simultaneous Multi-Threading in POWER5
►
Each chip appears as a
4-way SMP to software
Simultaneous Multi-Threading
FX0
►
►
Processor resources
dynamically optimized for
enhanced multithreading
performance
Dynamic switching between
single and multithreaded
mode
FX1
FP0
FP1
LS0
LS1
BRX
CRL
Thread 0
active
Thread 1
active
© 2004 IBM Corporation
Dynamic Power Management
Reduces power automatically – no program
intervention required and no performance impact
Two components: switching power and leakage power
►
Switching power reduction:
 Extensive fine-grain, dynamic clock-gating
►
Leakage power reduction
 Minimal use of low Vt devices
© 2004 IBM Corporation
No Power
Management
Dynamic Power
Management
Single
Thread
Simultaneous
Multi-threading
Photos taken with
thermal sensitive
camera while
prototype POWER5
chip was
undergoing tests
Simultaneous Multi-threading with dynamic power management reduces
power consumption below standard, single threaded level
© 2004 IBM Corporation
Reliability, Availability, Serviceability
► POWER4
drove unscheduled outages to near zero
► POWER5
designed to significantly reduce scheduled
outages
 Adds dynamic firmware upgrades
 Allows for concurrent CEC maintenance
►…
while at the same time enhancing basic reliability
 Full ECC on chip interconnections including address and
tag
 Additional centralized resource redundancy
© 2004 IBM Corporation
POWER5: Delivers system performance and
value through leadership technology
Highest Value / Lowest Risk
Lower
TCO
Superior
Availability
Superior
Flexibility
Higher
Performance
Leading Technology
© 2004 IBM Corporation