Transcript Commissioning the ATLAS Silicon Microstrip Tracker

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ATLAS and ID
SCT
Commissioning
Integration
Latest Runs
Conclusions
Commissioning the ATLAS
Silicon Microstrip Tracker
Jose E. Garcia
Université de Genève
for the Atlas SCT collaboration
IPRD08 - Siena
ATLAS Detector
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ATLAS and ID
SCT
Commissioning
Integration
Latest Runs
Conclusions
ATLAS is being assembled to
exploit the 14TeV pp collisions at
the LHC
The Inner Detector forms the heart of
the ATLAS experiment. The closest to
the interaction point.
• Pixel Detector
• Semiconductor Tracker (SCT)
• Transition Radiation Detector (TRT)
Jose E. Garcia
IPRD08 - Siena
Semi-Conductor Tracker
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ATLAS and ID
SCT
Commissioning
Integration
Latest Runs
Conclusions
• 61 m2 of silicon with 6.2 million readout channels
• 4088 silicon modules arranged to form 4 Barrels and 9+9 Disks
• Barrels : 2112 modules with acceptance || < 1.1 to 1.4
• Endcaps : 1976 modules with acceptance 1.1 to 1.4 <|| < 2.5
• Space point resolution r ~17m / Z ~ 580 m (23 m strip resolution)
• Radiation hard: tested to 2x1014 1-MeV neutron equivalent /cm2
• Material: 3% X0 per layer ( = 0)
Jose E. Garcia
IPRD08 - Siena
Silicon Modules
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ATLAS and ID
SCT
Commissioning
Integration
Latest Runs
Conclusions
• Back-to-back sensors, glued to highly thermally
conductive substrates for mechanical stability and
sensor cooling
• 40mrad stereo angle between sensors
• 1536 channels (768 on each side)
• Optical communication
• 5.6W/module (adding ~1W per sensor after 10
years LHC)
• Cooled to -25oC to limit sensor radiation damage
and -8oC ambient temperature.
• up to 500V sensor bias
• 2112 Barrel modules
• one module type
• 1976 EndCap modules
• 4 module types
Jose E. Garcia
IPRD08 - Siena
Front End Electronics
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ATLAS and ID
SCT
Commissioning
Integration
Latest Runs
Conclusions
128 channel ASIC with binary architecture
Radiation-hard DMILL technology
12 chips per module (6 each side)
glued to hybrid (Cu/polyimide flex circuit)
40MHz (25ns) clock
20ns front end shaping time
Redundancy scheme (chips, link, TTC)
Data Compression
PreAmp+Shaper
Circuit
Comparator
Readout Buffer
Edge-Detect circuit
Binary Pipeline (132 deep)
Test-Input
DAC
Threshold Voltage
• 3 pipeline bins read out, centered
on L1A trigger
v
“Shaped” input pulse
to Comparator
t
“Logic” output of
comparator
t
Jose E. Garcia
IPRD08 - Siena
Assembly Sites
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• 4 Assembly Sites
• Oxford
- Barrel
• Nikhef
- EndCap A
• Liverpool - EndCap C
• SR1 at CERN
ATLAS and ID
SCT
Commissioning
Integration
Latest Runs
Conclusions
Jose E. Garcia
IPRD08 - Siena
Installation Timeline
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ATLAS and ID
SCT
Commissioning
Integration
Latest Runs
Conclusions
Quarter 1
2006
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Quarter 2
Barrel in Pit
Quarter 3
Quarter 4
Quarter 1
2007
Quarter 2
Quarter 3
Quarter 4
EndCaps in Pit
Pixels in Pit
•Test Module connectivity and
performance comparing with surface data
Quarter 1
ID sealed
2008
Quarter 2
Quarter 3
ID operational in Atlas
Quarter 4
Jose E. Garcia
IPRD08 - Siena
Cooling Issues
• 3 ID compressors failed
• 100 kg of C3F8 lost and 900 contaminated
• Cooling plant cleaned up and broken parts
replaced
• Fortunately detector not affected
• Measures have been taken to prevent this to
happen again
Commissioning Tests
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ATLAS and ID
SCT
Commissioning
Integration
Latest Runs
Conclusions
• Electrical Connections
• Check LV arrives at modules: VDD, VCC, IPIN, IVCSEL
• HV current voltage scan
• Check temperature readings
• Optical Connections
• P-i-n current checks
• Light from fiber data measured at Redaout Driver (ROD)
• Check fiber connection and correct module mapping
• Calibration Tests
• Digital and Analogue functionality tested
• Gain curve, Noisy/Dead channel map
• Noise occupancy Tests
• Cosmic Tests
• Milestone 6 (M6) :
• Global commissioning run with ATLAS
Combined SCT and TRT track.
Jose E. Garcia
IPRD08 - Siena
Atlas Integration
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ATLAS and ID
SCT
Commissioning
Integration
Latest Runs
Conclusions
• Since middle of August cooling is back and running
stably for the detectors.
• SCT running fully powered since end August
• Standalone calibration was performed up to the first week of
September. From then SCT has been included in the Atlas data
taking
– Full Barrel and Endcap ROD readout
– Athena and ROS Level Monitoring
– Data Quality Monitoring
• Calibration and configuration changes are being made to improve performance.
Some modules were removed from due to readout issues. They will be back in
once they are properly adjusted. Approximate numbers:
– Barrel: 99.6% modules
– EndCaps (*): 97.8% modules
(*2 out of 72 cooling loops off, partially recoverable during shutdown)
• Around 97% configuration for stable readout in ATLAS
Jose E. Garcia
IPRD08 - Siena
Noise Occupancy
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ATLAS and ID
SCT
Commissioning
Integration
Latest Runs
Conclusions
Barrel Noise Occupancy at 150 V
• measured ~4.4 x 10-5
• Outer/middle NO of ~ 5 x10-5
• Inner type modules much lower due to
short strip length
• Values in agreement to measurements
from production, integration and
installation.
Jose E. Garcia
IPRD08 - Siena
Current issue: TTC link
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Some SCT channels generate no pin current (TX).
Suspect ESD damage.
ATLAS and ID
SCT
Commissioning
Integration
Latest Runs
Conclusions
ROD
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BOC
DATA
RX Ch
TX Ch
TTC
Currently affected
around
% ofor dead PIN
Broken
TX2.5
fibre
Clock and control from neighbouring
the modules
module Broken TX fibre or dead PIN
Clock and control from neighbouring
module
Currently we are using redundancy whenever possible (this is not possible where
two adjacent modules have zero pin current).
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Broken TX fibre or dead PIN
Clock and control from neighboring
module
If a few channels in a specific TX plugin are lost, it will be needed to change them.
o Plugins can be replaced at the USA15. Newly manufactured plugins are being
tested.
o
Jose E. Garcia
IPRD08 - Siena
Timing In with ATLAS
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ATLAS and ID
SCT
Commissioning
Integration
Latest Runs
Conclusions
• Apply global trigger delay offset on top of the 4088 individual delays,
and scan offset to look for increase in number of coincidental hits, increasing the
number of space-points and tracks.
• Reading 3 bunch crossings (3 x 25 ns clock cycles).
• Scans were done and SCT was timed in using cosmics before first beam and
continued after
0
1
X
• LATER (with beam!): When roughly timed in, start fine delay (steps of 280ps) to tune
relative bin occupancies and optimise hit efficiency. Fine scan delay scan with different
offsets for each module
Jose E. Garcia
IPRD08 - Siena
First Beam (10th Sept)
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SCT EndCaps at 20 V
during the first beam
ATLAS and ID
SCT
Commissioning
Integration
Latest Runs
Conclusions
Many tracks and space-points seen
during the circulating beam
Jose E. Garcia
IPRD08 - Siena
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ATLAS and ID
SCT
Commissioning
Integration
Latest Runs
Conclusions
Combined Tracks: SCT + Pixels
Data taking is ongoing 24/7 with the rest of the sub-systems.
First tracks seen with hits in pixels
and SCT combined
Jose E. Garcia
IPRD08 - Siena
Alignment with Last Cosmics Data
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The residuals for the SCT barrel show a
behavior similar to the M6 results.
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ATLAS and ID
SCT
Commissioning
Integration
Latest Runs
Conclusions
The residuals for the SCT barrel show a
behaviour similar to the M6 results.
Hits on tracks for barrel layers
SCT
Level 1
Barrel
EndCap
Level 2
Barrel layers
EndCap disks
Level 3
Barrel modules
EndCap modules
Jose E. Garcia
IPRD08 - Siena
Conclusions
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ATLAS and ID
SCT
Commissioning
Integration
Latest Runs
Conclusions
• SCT running fully powered since beginning of September with 97%
configuration for stable readout in ATLAS after the first round of readout
adjustments.
• Integrated the full SCT into ATLAS combined partition
• Observed first beam and used beam splashes to get first timing (on
endcaps)
• Currently ongoing cosmics runs for:
– Timing studies
– Alignment
– DAQ, DCS and Monitoring tuning up
– Improvement on module calibration
Jose E. Garcia
IPRD08 - Siena
Backup Slides
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ATLAS and ID
SCT
Commissioning
Integration
Latest Runs
Conclusions
Backup
Jose E. Garcia
IPRD08 - Siena
Timing In
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ATLAS and ID
SCT
Commissioning
Integration
Latest Runs
Conclusions
Backup
Trig
ROD
FINE
Compensate for different
propagation delays of
C&C from BOC to module
(which varies from 380ns
to 446ns)
• 4088 individual delays
from 0 to 66ns
Jose E. Garcia
… x48
FINE
FINE
ROD Crate
BOC coarse delay
Up to 32 clock cycles
IPRD08 - Siena
BOC fine delay up to
35ns in 280ps steps
Fibres to modules
FINE
Optical Communication
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ATLAS and ID
SCT
Commissioning
Integration
Latest Runs
Conclusions
Backup
Jose E. Garcia
IPRD08 - Siena