Transcript Digital Logic Design

Digital Logic Design
Lecture # 14
University of Tehran
Outline
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Review of Lecture #13
PLA
PAL
Structure of PROM’s Transistors
MSI Parts as a ROM
Cascading ROMs
Review of Lecture #13

Let us continue our discussion of programmable
devices. We saw the structure of a ROM with 4
inputs that had 16 lines entering its OR plane from
the AND plane. The AND plane can actually be
considered a 4-to-16 DCD as seen in the following
figure:
A B C D
0
...
AND
OR
15
w x
y
z
Review of Lecture #13
(continued…)
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We saw that no minimization was done when
realizing functions with ROMs, because all minterms
were produced in the fixed AND plane.
PLA
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Consider the following truth table:
A
0: 0
B
0
C
0
D
0
w
1
x
0
y
1
z
1
0
0
0
1
0
1
0
0
3: 0
0
0
1
1
0
1
1
1
0
0
1
0
0
5: 0
1
1
0
0
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
1
0
0
0
1
0
0
8: 1
9: 1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
1
0
1
11: 1
1
0
0
1
1
0
0
1
1
0
0
1
13: 1
14: 1
15: 1
1
1
1
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
0
0
1
0
1
1
1:
2:
4:
6:
7:
10:
12:
1
1
1
0
0
0
0
PLA (continued…)
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Note all minterms are used in the realization of a
function, and so minimizing this truth table using 4
variable KMs can be useful. Consider the following
minimization:
AB
CD
00
01
00
1
0
1
0
5
0
3
10
0
AB
CD
00
01
1
10
y
1
1
1
1
4
12
1
5
0
3
0
1
7
1
0
1
01
0
0
z
1
0
10
x
1
0
12
0
5
0
0
1
1
1
9
0
15
0
6
0
8
13
7
10
11
0
4
1
2
0
11
14
01
1
10
1
0
00
3
10
0
9
15
6
0
11
11
1
14
00
9
15
0
6
CD
8
13
AB
0
0
1
0
8
13
7
2
10
1
1
10
1
12
5
10
11
0
0
1
11
1
01
4
3
11
0
2
1
0
14
0
01
11
01
1
10
0
00
0
11
1
00
0
00
9
15
6
1
1
0
CD
8
13
7
2
1
12
AB
10
11
1
4
1
11
We will show why
these 1s are mapped
like this later on
01
1
11
0
14
1
10
w
PLA (continued…)
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In the minimization method shown in the last slide,
the number of variables used in a term is of no
importance. What we are looking to do in this
minimization is to share product terms between the
different functions thus being able to decrease the
number of rows in our AND plane. Doing this the
shown truth table can be realized as shown in the
next slide.
PLA (continued…)
A
B
C
D
w
x
y
z
_ _
BCD
_
ABD
___
ABC
_
ABCD
__
ABC
ABC
__
ABCD
_ _
ABCD
__
CD
_
ABCD
_
_
ABCD
_
_
ABCD
__
_
ABCD
PLA (continued…)
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The reason we don’t look for decreasing the number
of literals in our product terms is rather obvious as
there is no hardware difference. What we gain in
this procedure is better layout and less rows which
can be better observed in functions of a larger
number of variables. These structures are called
PLAs.
AND
OR
ROM Fixed
Prog.
PLA
Prog.
Prog.
PLA (continued…)
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We should see PLAs as structured logic components
helping us with a reduction of size in comparison to
the more general-purposed ROM ICs.
Nowadays PLA programmers use other techniques
such as column sharing in order to decrease the size
of PLAs even more.
PAL
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There is also a third kind of programmable device
with a fixed OR plane and a programmable AND
plane. An example of this structure called a PAL
structure can be seen below:
Feedback
line
A
B
C
D
A BCD  AB  C D
C D  f BC  ABC
f  AB  C D  BCD
permanent
connection
f
programmable
connection
PAL (continued…)
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As you can see in the last figure, PALs give us the
ability to share certain product terms between two
particular functions. Another choice PALs give us in
order to realize larger functions in the ability to
feedback an output of an OR gate back into the AND
plane and use it as a part of a larger function. It
must be noted that a feedback line can itself be used
as an output.
PAL (continued…)
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PALs do have a benefit with respect to PLAs
alongside all the restrictions they bring for realization
of a function and that is better timing. This is
because there is less delay on the OR gates of a PLA
because of the fixed and rather small number of
inputs to each OR gate.
Structure of PROM’s
Transistors
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Let’s see the kind of transistors that are used in
PROMs. These transistors are called floating gate
transistors and are structured as shown below:
floating gate
diff
main gate
diff
Structure of PROM’s
Transistors (continued…)
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When such a transistor is to be disabled the floating
gate is given a high voltage that brings electrons
from the two diffusion areas into it, giving it a
negative charge and thus disabling the gate. Ultra
violet light can be used to send these electrons back
to the diffusion area.
MSI Parts as a ROM
Let’s consider a 2764: In this figure the VPP and PFM
pins are used when programming the package. This
package has 13 inputs that gives us 213*8 memory
locations. That is 213 addresses pointing to 8 bit
2764
words.
vpp
pfm
...
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A0
A1
A12
CS
OE
o0 o1
o7
...
MSI Parts as a ROM
(continued…)
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The output lines are also used as input lines with the
use of three state buffers as can be seen. When
both CS and OE signals are 0, these pins act as
output and otherwise can be inputs for programming.
ENB
ENB
ENB
ENB
CS
OE
Cascading ROMs
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Standard packages need to have the ability to
cascade. ROMs are cascaded in 2 styles:
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The following method is called horizontal cascading that
expands our word length:
13
0
1
0
1
vpp
pfm
13
vpp
pfm
13
2764
2764
8
8
CS
OE
16
Cascading ROMs (continued…)
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The other one is called vertical cascading that expands our
address space to 14 lines that is 16k, as shown in the
following figure:
A13 A12
…
A1 A0
0
1
13
vpp
pfm
2764
OE
CS
8
0
1
13
vpp
pfm
2764
OE
CS
8
8
Cascading ROMs (continued…)
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Note that the programming of these packages must
be done each on its own and not in cascaded form.