Transcript Notes

Architecture /Circuit Design--Levels and Views
SURVEY OF STUDENT BACKGROUNDS:
If you were not in first class, please turn in the
following information:
1. your name
2. undergrad: major / year of graduation________
grad: research area / m.s. or ph.d. / advisor if
known_________________________________
3. please list any previous experience / courses in
hardware design and any design tools which you
have used previously (altera, xilinx, magic, vhdl, ….)
(Note: "no previous experience" is acceptable here-I need accurate information about the background
of each student in the class)
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Topics to be discussed:
 the hardware design crisis
 circuit views and levels
 complete sets
2
"design productivity crisis“:
logic trans/chip
(M)
10,000
K-trans/
staff-mo
100,000
1,000
10,000
100
1,000
10
100
1
10
0.1
1
0.01
0.001
1980
0.1
85
90
95
00
0.01
05
2010
productivity
growth ~ 21%/yr
circuit complexity growth
~58%/year
("Moore's Law": # transistors on a chip doubles about
every 18 months; what about productivity?)
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--hardware capability increases at a rapid rate
--to harness this capability, we must employ design
reuse, "IP" (intellectual property), abstraction
--we need "smarter" tools to allow us to succeed at
this task
some current strategies and emerging trends:
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 hardware design languages ("HDL's"): leaders are
VHDL, Verilog--increase design capability through
abstraction, information hiding, "smart" "compilers"
 hardware/software codesign: design hardware and
software in parallel; postpone decision about where some
components will be implemented until late in the design
process--abstraction
 "SOC"--system on a chip--digital, analog, other energy
domains
 intelligent processing, etc.--continue to move software
functionality to hardware to improve processing
efficiency
 reconfigurable computing--change hardware
configuration dynamically to maximize efficiency of
processing
 "levels and views"--focus on particular parts of the
problem--choose the highest level of abstraction possible
for the problem you are solving
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LEVELS &
VIEWS:
Behavioral / Functional View
Performance Specs.
HIGH
LEVEL
Algorithms
Register Transfers
Boolean Logic, FSM's
Transfer Functions, Timing
Transistors, Contacts, Wires, Vias
Gates, Flip-flops, Cells
Registers, ALU's, MUX's
Hardware Modules
Processors, Memory,
Switches, Buses
Structural View
Layout Geometry
Modules, Cells
Floor Plans
Clusters
Physical Partitions
Physical View
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Example (half
adder, based
on Figure 4,
Chapter 13,
Handbook of
Mechatronics
and additions)
--VHDL entity
entity HALFADDER is
port (A,B: in bit;
S,COUT: out
bit);
end ADDER;
TRANSISTOR
(PHYSICAL)
LIBRARY
COMPONENT
(PHYS. / BEHAV./
STRUCT.)
NETLIST
(STRUCTURAL)
n1: a b o1
n2: a c o2
n3: o1 o2 o3
--VHDL ARCHITECTURE
(STRUCTURAL)
--VHDL ARCHITECTURE (BEHAVIORAL/DATAFLOW):
architecture A of HALFADDER is
component XOR
port (X1,X2: in bit; O: out bit);
end component;
component AND
port (X1,X2: in bit; O: out bit);
end component;
architecture PROCESS_BEHAVIOR of HALF ADDER is
begin
SUM_PROC: process(A,B)
begin
if (A = B) then
S <= '0' after 5 ns;
else
S<= (A or B) after 5 ns;
end if;
end process SUM_PROC;
CAR_PROC: process (A,B)
begin
case A is
when '0' =>
COUT <= A after 5 ns;
when '1' =>
COUT <= B after 5 ns;
when others =>
COUT <= 'X' after 5 ns;
end case;
end process CAR_PROC;
end PROCESS_BEHAVIOR;
begin
G1: XOR
port map (A,B,S);
G2: AND
port map (A,B,COUT);
end A;
--VHDL ARCHITECTURE (BEHAVIORAL)
architecture CONCURRENT of HALF ADDER is
--this is a behavioral description ("delay" = 5 ns here)
--it does NOT imply that XOR or AND gates will be
used in the implementation
begin
S <= (A xor B) after 5 ns;
COUT <= (A and B) after 5 ns;
end CONCURRENT;
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Views (Domains):
Behavioral/Functional: we describe the functionality
of the circuit without necessarily specifying how this
functionality will be achieved
Physical: we specify the actual physical parts of the
circuit and where they will be located with respect to
one another
Structural: intermediate between physical and
behavioral. It provides an interface between the
functionality specified in the behavioral domain,
which ignores geometry, and the geometry specified
in the physical domain, which ignores functionality.
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Goal: choose the most appropriate level / view for
each implementation step. Note that these steps
apply to systems consisting of hardware alone,
software alone, or a combination of the two:
 analysis of requirements
 specification
 design
 simulation
 fabrication / implementation
 test
 maintenance
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Some examples:
--VHDL entity
Behavioral/ Functional: this allows us to think
entity HALFADDER is
clearly about WHAT the system needs to do, what
port (A,B: in bit;
S,COUT: out
inputs are needed, and what outputs must be
bit);
provided. This is a useful way to express
end ADDER;
specifications and also to assist with "black box"
--VHDL ARCHITECTURE (BEHAVIORAL/DATAFLOW):
testing, for example.
--VHDL ARCHITECTURE (BEHAVIORAL)
architecture CONCURRENT of HALF ADDER is
--this is a behavioral description ("delay" = 5 ns here)
--it does NOT imply that XOR or AND gates will be
used in the implementation
begin
S <= (A xor B) after 5 ns;
COUT <= (A and B) after 5 ns;
end CONCURRENT;
architecture PROCESS_BEHAVIOR of HALF ADDER is
begin
SUM_PROC: process(A,B)
begin
if (A = B) then
S <= '0' after 5 ns;
else
S<= (A or B) after 5 ns;
end if;
end process SUM_PROC;
CAR_PROC: process (A,B)
begin
case A is
when '0' =>
COUT <= A after 5 ns;
when '1' =>
COUT <= B after 5 ns;
when others =>
COUT <= 'X' after 5 ns;
end case;
end process CAR_PROC;
end PROCESS_BEHAVIOR;
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Structural: at this level we can carry out logic
optimization and state minimization. We can also
plan layout in terms of the major modules which will
make up the circuit. This step is called floorplanning.
We can sometimes also utilize partitioning and
compaction to minimize the structures which must be
implemented. In general, at this step we are
concentrating on logic minimization rather than
physical minimization. In some cases, however, for
example with PLA-type systems, these two types of
minimization can occur concurrently.
--VHDL entity
entity HALFADDER is
port (A,B: in bit;
S,COUT: out
bit);
end ADDER;
--VHDL ARCHITECTURE
(STRUCTURAL)
architecture A of HALFADDER is
component XOR
port (X1,X2: in bit; O: out bit);
end component;
component AND
port (X1,X2: in bit; O: out bit);
end component;
begin
G1: XOR
port map (A,B,S);
G2: AND
port map (A,B,COUT);
end A;
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Physical: at this point we are concerned with the
actual physical parameters of the circuit. We may,
for example, consider different placements of
particular wires or transistors to minimize circuit
area. We may also consider sizing of individual
transistors or sequences of transistors to produce
faster circuits. We also have to consider questions of
fan-in and fan-out (although these questions can also
be addressed to some extent at the structural level).
We must consider what material each piece of the
circuit will be made from (for example, which pieces
of wire will lie in each of the two metal layers usually
provided in a CMOS circuit), and we must make
determinations about resistance, capacitance, power
usage, and latch-up.
TRANSISTOR
(PHYSICAL)
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In this course we will be working mostly at the
BEHAVIORAL and STRUCTURAL levels.
We will rely on the Altera design tools to do
MOST of the physical design and optimization.
Here we will quickly review the basic
STRUCTURAL building blocks commonly used-complete sets, muxes, demuxes, adders, flip-flops,
counters, registers, memory, I/O .
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Complete Sets.
In some situations it is efficient to represent all Boolean functions
in terms of a (small) set of fundamental functions. For example, if
we are building hardware devices, it would make our work easier
if we could just design two or three different ones and then build
everything else out of these few. Such a set is called a complete
set. For Boolean functions of two variables, there are three
complete sets that are commonly used:
a. AND, OR, NOT
b. NAND
c. NOR
Using properties of boolean algebra, it can be shown that a
complete set for two inputs will also be a complete set for any
number of inputs. this fact will turn out to be especially useful
when we consider physical implementations of these functions.
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Proof that AND,OR, NOT is complete for 2-input boolean functions: we can give
a straightforward truth table proof of this fact. For n > 2, how big does our truth
table need to be? If we have N inputs, A1,…,AN, then each Ai, 1 <= i <= N, can
take on two values, 0 or 1, so there are 2N rows in an N-input truth table. A
Boolean function of A1,…,AN is defined by assigning a 0 or 1 value to each row.
So there must be 2**(2N) possible functions. For N = 2, there are 2**(22) = 2**4
= 16. We get the following table:
AB f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff
00 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
01 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
10 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
and we can represent functions f0--ff as follows:
f0=A(~A) f1=AB
f2=A(~B)
f3=A
f4=(~A)B f5=B
f6=A(~B)+(~A)B f7=A+B
f8=~(A+B) f9=(~A)(~B)+AB fa=(~B)
fb=A+(~B)
fc=~A fd=(~A)+B fe=~(AB)
ff=A+(~A)
The representation is not necessarily unique, e.g.,
f0 = A AND ~A = B AND ~B
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For actual implementation, the type(s) of gates
chosen will be an important factor. We typically
want as few gates as possible, connected together as
simply as possible. The modules we describe here
will be structural, rather than physical, but choices
made in the structural view may, when automated
design tools are used to translate the design to the
physical view, also affect the physical representation.
Common goals:
 minimize the number of gates
 minimize area taken up by wires (this is becoming more and more important as
circuit "feature size" decreases)
 keep fan-in and fan-out small
 choose regular patterns which are easily replicated
 minimize the length of the critical path (the path, not necessarily unique, along
which a signal through the circuit will take the longest time to propagate).
Propagation time will be the sum of the times through each gate plus the time
to propagate along the connecting wires.
 Minimize power usage
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