Transcript Silicon Deposition

Wafer Fabrication
Nam Nguyen
Todd Allen
Dipesh Chasmawala
Daniel Canales
Inoke Hemaloto
Cheng Hsiao
Overview (1/3)
• Crystal Structure
– Monocrystalline
• An existing monocrystalline silicon serves as
a seed for uniform crystal growth
– Polycrystalline
• Consists of a multitude of fine-grained gray
crystals
Overview (2/3)
• Diffusion
– Process in which the dopants diffuse to a certain
junction depth and forms a doped region
– Deposition
• Heat the wafer and external source of dopant atoms
to form a shallow heavily doped region
– Drive
• External dopant source is removed and wafer is
heated for a prolonged period of time to drive the
dopants deeper
Overview (3/3)
• Ion Implantation
– Accelerates dopant atoms so that they can
penetrate several microns of the silicon crystal
• Causes damage to the crystal lattice that
must be repaired by annealing
Silicon Deposition
What is silicon deposition?
• A film of pure or doped silicon that is
‘grown’ onto an existing wafer.
• There are 2 types of crystal lattices formed
from the process. Each lattice depends on
the crystal structure that the silicon is
applied to.
The 2 Types of Crystal Formed
• Mono crystal
• Poly crystal
• Requires contact with
the mono crystalline
wafer to act as a ‘seed’
for crystal growth
• Consists of fine grains
of silicon formed
when no contact with
the underlying
crystalline lattice is
made
Epitaxy (epi)
• Epitaxy is the type of silicon deposition that
results in single crystal growth due to
contact with a suitable crystalline lattice.
• Epitaxy usually performed using the wafer,
for economic reasons.
Different Methods for Growing
an epi Layer.
• There are 2 types of epitaxy described in
our textbooks
• The first is liquid-phase epitaxy
• The second is low pressure chemical vapor
deposition (LPCVD)
• There are several other methods for
producing an epi layer
Liquid-Phase Epitaxy
• Molten semiconductor material is poured
directly onto wafer
• After allowing material to cool for a
specified time the non-bonded material is
wiped away
• Wafer must then be reground and polished
for further processing
Drawbacks to Liquid-Phase
Epitaxy
• Considered as economically undesirable
due to the costs incurred to repolish the
wafer after each step
• Also it is difficult to accurately control the
thickness of the epi layer in this process
LPCVD Method
• Wafers are mounted on an inductively
heated block and a mixture of
Dichlorosilane and hydrogen gas is passed
over the wafers. These gases react at the
wafer surface to create a slow growing layer
monocrystalline silicon.
Advantages of LPCVD Method
• The rate of silicon growth can be regulated by
varying the temperature, pressure, and gas
mixture.
• No polishing is required as the vapor deposited
silicon will faithfully reproduce the structure of
the underlying lattice.
• The epitaxial film can also be doped by adding
small amounts of gaseous dopants such as
phosphine or diborane.
Advantages / Disadvantages of
Epitaxy
• ADVANTAGES
• Create stacks of
differently doped
layers useful in the
creation of bipolar
transistors
• Create buried layers
• DISADVANTAGES
• Time required to grow
silicon layers
• High cost of
equipment used in
process
Buried Layers
• Epitaxy can create layers of differently
doped silicon useful in the creation of
bipolar transistors.
• By using epitaxy over a N+ region a heavily
doped emitter region with low emitter to
base resistance is created.
NBL Shadow
• A slight surface imperfection arises from
the oxidation caused during the annealing of
the N+ implant
• As the epitaxial layer grows this
imperfection will be reproduced at the end
of the growth cycle
Polysilicon Deposition
• Formed when no seed lattice is available,
the silicon will form in small grains. Grain
size depends upon conditions of the
deposition as well as heat treatments.
NBL Shadow
• The imperfection will maintain the same
geometry as the substrate imperfection but
may be moved laterally, known as pattern
shift
• Following photomasks can use the NBL
shadow for alignment purposes. This
requires an offset due to the pattern shift
Advantages / Disadvantages of
Polysilicon Deposition
• ADVANTAGES
• Withstand high
temperatures (better
then al) for annealing
source and drain
• Create narrow
resistors with less
parasitics
• Can be used as
metallization layer
• DISADVANTAGES
• Grain boundaries
represent lattice
defects which allow
high leakage current,
not used for PN
junctions
Metallization
• The active elements of an integrated circuit
are connected by patterned wiring
• The wiring is consists of layers of metal and
polysilicon separated by insulators, usually
deposited oxides
Metallization Process
• A layer of oxide is grown or deposited over
the entire wafer
• A photo etching process removes the oxide
from areas desired for metallization contact
• A thin film of metal is then applied
• The metal is etched off
• An integrated circuit may have multiple
metallization layers to reduce cost
Deposition and Removal of Al
• Most metallization systems employ Al or Al
alloys for the primary interconnection layers
• Al almost conducts as well as Cu and Ag
and will readily deposit in thin films that
adhere to all the materials used in the
fabrication of integrated circuits
Sintering
• Sintering creates Ohmic contacts
• A brief period of heating will make a thin
film of Al-doped silicon (sintering)
• The Al-Si alloy causes a heavily doped Ptype diffusion that bridges the P-type silicon
• Also form Ohmic contact with heavily
doped N-type silicon
Sintering Failures
• Sintering causes some Al to dissolve into
the Si
• Some Al diffusions are so thin that the Al
can erode completely, called contact spiking
• CS was first observed in the emitter regions
of NPN transistors so CS is also known as
emitter punchthrough
• CS is minimized by replacing Al with a
saturated Al-Si alloy
Electromigration
• Caused by heavy current flow, carriers
flowing through the metal collide with the
lattice atoms
• At current densities of several million amps
per cm2, impacts will start to cause the
metal atoms to move
• As the atoms move, small gaps are made
that eventually combine to cause an open
connection, this is call electromigration
• A fraction of a percent Cu added improves
resistance to electromigration by an order of
magnitude
Step Coverage Problem
• As chips become more densely packed, the
sidewalls of contacts and vias has become
progressively steeper
• Evaporated Al does not deposit
isotropically, it thins where it crosses oxide
steps
Step Coverage Techniques Reflow
• Step coverage is greatly improved if the
slope of the side wall is moderated.
• By reheating the wafer the oxide will melt
and the sidewalls form a sloped surface
• Pure oxide melts at too high a temperature
so it is doped with either/and P and B
• If P doped is called phosphosilicate (PSG),
if B doped is called borophosphosilicate
(BSG)
Drawback to Reflow Solution
• Al cannot be applied before reflow as the
temperatures involved are to high
• Reflow is effective for the first-level metal
only
• Use of refractory barrier metals is used in
subsequent metal layers
Refractory Barrier Metal
• Metals chosen for their isotropic deposit on
sidewalls (molybdenum Mo, tungsten W,
and titanium Ti)
• Refractory barrier metals have high melting
temps and are unsuited for evaporation
deposition like Al
• Sputtering is used for low temp deposit
Refractory Barrier Metals
• RBM’s posses high resistances and cannot
be deposited thickly as easily as Al
• Use of a thin film of RBM under Al ensures
suitably low resistance
• RBM’s are resistant to electromigration
• RBM’s practically eliminate emitter punch
through so there is little need for Al-Si or
Al-Si-Cu alloys
Sillicides
• Elemental SI reacts with many metals
• Can for low-resistance Ohmic contacts or
Schottky diodes
• Sillicides have lower resistances than the
most heavily doped Si
• Can withstand high temperature treatments
• Useful in MOS transistors
Interlevel Oxide
• Used to insulate metal layers from one
another
• Vias can be etched through the ILO
• Relatively thick ILO can reduce parasitic
capacitances
• Can cause step problems in vias
• No reflow after Al deposited so RBM’s are
often used to improved step coverage
Interlevel Nitride
• Used to create high capacitance-per-unitarea films
• Dielectric constant 2.3 times that of oxide
• More prone to pinhole formations that
reduce the max voltage
• Combination of stacked silicon nitride and
oxide are used for dielectric constant
between oxide and silicon nitride
Protective Overcoat
• Al is fragile to mechanical stress
• Al and the underlying Si are vulnerable to
certain chemical contaminants
• The protective overcoat (PO) forms a seal
against mechanical and chemical threats
• Most often made from compressive nitride
films, some are heavily doped
phosphosilicate glasses
Assembly/Packaging
Assembly (1/3)
• Performed in an assembly/test site
• Finished wafer
– Each square represents a completed integrated
circuit
– Some of the locations in the array are occupied
by process control structures and test dice
Finished Wafer
Process Control Structures
• Extensive arrays of transistors, resistors,
capacitors, diodes, strings of contacts, and vias
– Used to evaluate the success or failure of the
manufacturing process on the wafer by
automated testing equipment
– Standardized so the same structures are used for
a wide range of products
Test Dice (1/3)
• Used to evaluate prototypes of an integrated
circuit
• Specific to a given product
• Dedicated test metal mask allows probing of
specific components and subcircuits that would be
difficult to access on the finished die
Test Dice (2/3)
– Created by adding a few more layers to the
database containing the layout of the integrated
circuit (e.g., test metal, test nitride)
• Layers create a separate set of reticles that
are used to expose a few selected spots on
the stepped working plate
– These locations become unnecessary when
testing is completed
Test Dice (3/3)
• Wafers created by direct-step-on-wafer (DSW)
processing rarely include any test dice because at
least one test die must be included in every
exposure
– If they are included then the test dice will most
likely be replaced with product dice after
testing is completed to improve the die yield
Assembly (2/3)
• After the wafers are tested to ensure the process
was performed correctly, each die is individually
tested to determine its functionality
– Testing of each die typically requires less than
three seconds
– The percentage of good dice depends on the
size of the dice and the complexity of the
process
• Most products yield 80%, some in excess of
90%
Assembly (3/3)
• Wafer probing uses probes to make contact with
specific locations on the interconnection pattern of
the integrated circuit through holes in the
protective overcoat and test each individual die to
determine its functionality
– Probes are mounted on a probe card that is
lowered until the probe comes in contact with
the wafer to be tested
– The individual dice are sawn apart using a
diamond-tipped saw blade, then separated for
mounting and bonding
Mounting (Leadframe 1/2)
• The first step of packaging an integrated circuit is
mounting it on a leadframe
• Leadframe Diagram
– The leadframe consists of a rectangular mount
pad and a series of lead fingers
– They are either stamped out or etched using
photographic techniques
– Usually consists of copper or a copper alloy
plated with tin or a tin-lead alloy
Leadframe Diagram
Etched Leadframe
Pressed Leadframe
Mounting (Leadframe 2/2)
– Copper is not an ideal material because it has a
different coefficient of thermal expansion than
silicon
• Differential expansion of the die and the
leadframe causes mechanical stresses that
damages the performance of the die
– Most of the materials that possess coefficients
of expansion similar to silicon have inferior
mechanical and electrical properties
– Nickel-iron alloy (Alloy-42) is the most
common
Mounting (Epoxy Resin)
• The die is usually mounted to the leadframe using
an epoxy resin
• Sometimes the resin is filled with silver powder to
improve thermal conductivity
– Helps reduce the stresses produced by thermal
expansion of the leadframe and die
• Alternate methods provide superior thermal union
between the silicon and the leadframe, but at the
cost of greater mechanical stress
Mounting (Gold Preform)
– The backside of the die can be plated with a
metal or a metal alloy and soldered to the
leadframe
– Rectangle of gold foil called a gold preform can
be attached to the leadframe; heating the die
causes it to alloy with the gold preform to
create a solid mechanical joint
• Both allow excellent thermal contact and
produce an electrical connection that can be
used to connect the substrate of the die to a
pin
Bonding (1/2)
• The next step is to attach bondwires to them
• Can only be performed in areas of the die where
the metallization is exposed through openings in
the protective overcoat called bondpads
• Performed by high-speed automated machines that
use optical recognition to determine the locations
of the bondpads
– Employs gold wires ranging from 20 µm to 50
µm for bonding
– Only one diameter and type of wire can be
bonded at a time
Bonding (2/2)
– Multiple 25 µm wires bonded in parallel can
carry higher currents or provide lower
resistances without requiring a second bonding
pass for larger-diameter wire
Ball Bonding (1/2)
• Most common technique for bonding gold wire is
ball bonding
– Ball Bonding Diagram
• Bonding machine feeds the gold wire
through a capillary
• Hydrogen flame melts the end of the wire to
form a ball
• The capillary presses down against the
bondpad
• Gold ball deforms under pressure, and the
gold and aluminum fuse to form a weld
Ball Bonding (2/2)
• Capillary lifts, moves to lead finger, and
presses the gold wire against the lead finger
forming another weld
– This bond is called a stitch bond because
of the absence of a ball
• The hydrogen flame then passes through the
wire, fusing it into two
• Ball bonding requires a square bondpad
approximately three times as wide as the
diameter of the wire
Ball Bonding Diagram
Wedge Bonding (1/2)
• Wedge bonding is another technique used for
aluminum wire
– When the capillary brings the wire close to the
bondpad, a small, wedge-shaped smashes it
against the pad to create a stitch bond
– Process is repeated at the lead finger and the
tool is then held down against the lead finger
while the capillary moves up causing the
aluminum wire to snap
Wedge Bonding Diagram
Wedge Bonding (2/2)
• Wedge bonding requires a rectangular bondpad
– Bondpads must lie in the same direction as the
wedge tool
– Typically twice as wide and four times as long
as the diameter of the wire
Packaging (1/2)
• The next step is injection molding
– A mold is clamped around the leadframe and
heated plastic resin is forced into the mold from
below
– The plastic wells up around the die, lifting the
wires away from it forming loops
– The plastic resin forms a rigid block of plastic
Packaging (2/2)
• After the molding process, the leads are trimmed
and formed to their final shapes
• Done by using a pair of specially shaped dies
that simultaneously trim away the links
between the individual leads and bend the to
the required shape
– Completed circuits are labeled and packaged in
tubes, trays, reels and shipped off