Transcript CMOS VLSI Design CMOS VLSI Design 4th Ed.

Lecture 14:
Wires
Outline
 Introduction
 Interconnect Modeling
– Wire Resistance
– Wire Capacitance
 Wire RC Delay
 Crosstalk
 Wire Engineering
 Repeaters
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CMOS VLSI Design 4th Ed.
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Introduction
 Chips are mostly made of wires called interconnect
– In stick diagram, wires set size
– Transistors are little things under the wires
– Many layers of wires
 Wires are as important as transistors
– Speed
– Power
– Noise
 Alternating layers run orthogonally
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CMOS VLSI Design 4th Ed.
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Wire Geometry
 Pitch = w + s
 Aspect ratio: AR = t/w
– Old processes had AR << 1
– Modern processes have AR  2
• Pack in many skinny wires
w
s
l
t
h
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CMOS VLSI Design 4th Ed.
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Layer Stack
 AMI 0.6 mm process has 3 metal layers
– M1 for within-cell routing
– M2 for vertical routing between cells
– M3 for horizontal routing between cells
 Modern processes use 6-10+ metal layers
– M1: thin, narrow (< 3l)
• High density cells
– Mid layers
• Thicker and wider, (density vs. speed)
– Top layers: thickest
• For VDD, GND, clk
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CMOS VLSI Design 4th Ed.
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Example
Intel 90 nm Stack
Intel 45 nm Stack
[Thompson02]
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[Moon08]
CMOS VLSI Design 4th Ed.
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Intel 45nm Stack
Layer
t (nm)
w (nm)
s (nm)
Pitch (nm)
M9
7000
17500
13000
30500
M8
720
400
410
810
M7
504
280
280
560
M6
324
180
180
360
M5
252
140
140
280
M4
216
120
120
240
M3
144
80
100
160
M2
144
80
100
160
M1
144
80
100
160
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Intel 45nm Stack
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CMOS VLSI Design 4th Ed.
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Interconnect Modeling
 Current in a wire is analogous to current in a pipe
– Resistance: narrow size impedes flow
– Capacitance: trough under the leaky pipe must fill first
– Inductance: paddle wheel inertia opposes changes in flow rate
• Negligible for most
wires
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CMOS VLSI Design 4th Ed.
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Impact of Interconnect
 Reduce reliability
 Affect performance
– Increase tp
– Increase energy dissipation
– Cause the introduction of extra noise sources
 Inductive effects usually ignored
 Resistive effects ignored if wire is short
 Interwire capacitance usually ignored if overlap is
small
 Wire capacitance is dominant
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CMOS VLSI Design 4th Ed.
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Wire Models
Capacitance-only
All-inclusive model
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CMOS VLSI Design 4th Ed.
Capacitance of Wire Interconnect
VDD
VDD
M2
Vin
Cg4
Cdb2
Cgd12
M4
Vout
Cdb1
Cw
Vout2
Cg3
M1
M3
Interconnect
Fanout
Simplified
Model
12
Vin
Vout
CL
CMOS VLSI Design 4th Ed.
Capacitance: The Parallel Plate Model
Current flow
L
Electrical-field lines
W
H
tdi
Dielectric
Substrate
cint 
13
 di
t di
WL
S Cwire
S
1


S  SL SL
CMOS VLSI Design 4th Ed.
Permittivity
14
CMOS VLSI Design 4th Ed.
Fringing Capacitance
(a)
H
W - H/2
+
(b)
15
CMOS VLSI Design 4th Ed.
Fringing Capacitance
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Fringing Capacitance
 Some other formulas




W

H
2

Cwire   diL 

 2t 

H
t di 2t di
di

ln
1
1 1 

t di 

 H 



Cwire
W 
W 0.25
H 0.5 
  diL   0.77 1.06  1.06  
t di 
tdi  

t di 

 This empirical formula is accurate to 6% for AR < 3.3

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Fringing versus Parallel Plate
(from [Bakoglu89])
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CMOS VLSI Design 4th Ed.
Wire Capacitance
 Wire has capacitance per unit length
– To neighbors
– To layers above and below
 Ctotal = Ctop + Cbot + 2Cadj
s

w
t 
Ctotal   0 l 2k vert  2khoriz  C fringe

h
s 
layer n+1
h2

w
Ctop
t
h1
layer n
Cbot
Cadj
layer n-1
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CMOS VLSI Design 4th Ed.
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Interwire Capacitance
fringing
20
parallel
CMOS VLSI Design 4th Ed.
Capacitance Trends
 Parallel plate equation: C = oxA/d
– Wires are not parallel plates, but obey trends
– Increasing area (W, t) increases capacitance
– Increasing distance (s, h) decreases capacitance
 Dielectric constant
– ox = k0
• 0 = 8.85 x 10-14 F/cm
• k = 3.9 for SiO2
 Processes are starting to use low-k dielectrics
– k  3 (or less) as dielectrics use air pockets
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CMOS VLSI Design 4th Ed.
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M2 Capacitance Data
 Typical dense wires have ~ 0.2 fF/mm
– Compare to 1-2 fF/mm for gate capacitance
400
350
300
M1, M3 planes
s = 320
s = 480
s = 640
s=
200
8
Ctotal (aF/mm)
250
Isolated
s = 320
150
s = 480
s=
8
s = 640
100
50
0
0
500
1000
1500
2000
w (nm)
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Impact of Interwire Capacitance
(from [Bakoglu89])
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CMOS VLSI Design 4th Ed.
Capacitance of Dense Wires
 An empirical equation is
Cwire
1.34

H 0.222  W 
H 
H 0.222  t di  
 W 




  diL1.15  2.80   0.06 1.66  0.14 
W 
 
t
t
t
t
t
 di 
 di 
 di  


  di 
 sp  
  di 

 Also, floating capacitors occur, which
– Create noise
– Affect performance
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CMOS VLSI Design 4th Ed.
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Wiring Capacitances
 We typically use simple models for capacitance,
given by
Cwire  Carea A  C perimeterP

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CMOS VLSI Design 4th Ed.
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Wiring Capacitances (0.25 mm CMOS)
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Diffusion & Polysilicon
 Diffusion capacitance is very high (1-2 fF/mm)
– Comparable to gate capacitance
– Diffusion also has high resistance
– Avoid using diffusion runners for wires!
 Polysilicon has lower C but high R
– Use for transistor gates
– Occasionally for very short wires between gates
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Wire Resistance
 r = resistivity (W*m)
r l
l
R
R
t w
w
 R = sheet resistance (W/)
–  is a dimensionless unit(!)
 Count number of squares
– R = R * (# of squares)
w
l
w
l
t
l
t
1 Rectangular Block
R = R (L/W) W
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w
CMOS VLSI Design 4th Ed.
4 Rectangular Blocks
R = R (2L/2W) W
= R (L/W) W
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Sheet Resistance
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CMOS VLSI Design 4th Ed.
Choice of Metals
 Until 180 nm generation, most wires were aluminum
 Contemporary processes normally use copper
– Cu atoms diffuse into silicon and damage FETs
– Must be surrounded by a diffusion barrier
Metal
Bulk resistivity (mW• cm)
Silver (Ag)
1.6
Copper (Cu)
1.7
Gold (Au)
2.2
Aluminum (Al)
2.8
Tungsten (W)
5.3
Titanium (Ti)
43.0
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Contacts Resistance
 Contacts and vias also have 2-20 W
 Use many contacts for lower R
– Many small contacts for current crowding around
periphery
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Copper Issues
 Copper wires diffusion barrier has high resistance
 Copper is also prone to dishing during polishing
 Effective resistance is higher
r
l
R
 t  tdish  tbarrier   w  2tbarrier 
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Example
 Compute the sheet resistance of a 0.22 mm thick Cu
wire in a 65 nm process. Ignore dishing.
2.2 108 Ω m
R 
 0.10 W /
6
0.22 10 m
 Find the total resistance if the wire is 0.125 mm wide
and 1 mm long. Ignore the barrier layer.
1000 m m
R   0.10 Ω/ 
 800 W
0.125 m m
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Skin Effect
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Skin Effect
 Define a skin depth, d, where the current falls to 1/e
of its nominal value.
r
d
fm
 Here, m is the permeability of the surrounding
dielectric and has a typical value of approximately
4 X 10-7for all dielectrics.
 For Al at 1 GHz, d = 2.6mm.
 To see the effect, assume a rectangular wire.
 Assume that the current flows only in the skin as
defined above
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Skin Effect
 The cross section is given by
A  2dW  2d H  2d   2W  Hd

H
W
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Skin Effect
 Using this cross sectional area,
r f  
fmr
2H W 
 We can define a frequency fs where the skin depth is
half the highest dimension of the conductor.

 It is not meaningful
to increase the dimensions
beyond that point for that frequency.
4r
fs 
2
mmax W ,H 
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Skin Effect
 For Al in SiO2, at 1GHz fs, the largest dimension
should be 5.2mm.
 Actual results show 30% increase in R due to skin
effect for a 20mm wire and 2% for a 1mm wire.
 One other thing to note is that the actual frequency
of the square wave should not be used.
 A sine wave whose rise and fall times equal to the
rise and fall times of the square wave will give more
accurate results.
 For 20% - 80% rise and fall, the equivalent
1
frequency is given by f 
8.65t rf
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Skin Effect
 As another example, choose copper in SiO2 with
20ps edge rates.
 f=5.8GHz, d = 0.99mm
 Note that the resistivity of metals drops at very low
temperatures.
 For example, an order of magnitude improvement at
77K (liquid nitrogen).
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CMOS VLSI Design 4th Ed.
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Inductance
 We will ignore inductance in this course
 Inductance causes voltage variations
di
V  L
dt
 Inductance causes extra impedance.
 Remember cl  m where
– c: capacitance
per unit length

– l: inductance per unit length
 : permittivity of the surrounding dielectric

 m: permeability of the surrounding dielectric
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Inductance
 Also, remember that
1
1
c0
c0
v



lc
m
 r mr
r

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Dielectric
r
Prop. Speed
(cm/ns)
Vacuum
1
30
SiO2
3.9
15
PC Board (epoxy
glass)
5.0
13
Alumina (ceramic
packages)
9.5
10
CMOS VLSI Design 4th Ed.
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Inductance
 How do we use this information?
 From a previous table,
c  Wx 30  2x40aF / mm
3.9x8.854 x10 12 x4 x10 7
l
c
c (aF/mm)
l (pH/mm)
W = 0.4mm
92
0.47
W = 1mm
110
0.39
W = 10mm
380
0.11

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Inductance
 Using
Rsh  0.075 W/sq
0.075
r
W/ mm
W




Equating the impedances, Z = wl
For a 1mm wide wire, r = Z at 30GHz.

Inductance is not an issue for now.
Typically, lower level metals are microstrips whose
inductances are given by
m0 8h w 
Ll
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ln   
2  w 4h 
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Inductance
 On-chip inductance is important for wires where the
speed of light flight time is longer than either the rise
times of the circuits or the RC delay of the wire.
 This can be expressed as
tr
2 L
l
R C
2 LC

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Inductance
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Inductance
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Lumped Element Models
 Wires are a distributed system
– Approximate with lumped element models
N segments
R
R/N
C
R/N
C/N
C/N
R
R
C
L-model
C/2
R/N
R/N
C/N
C/N
R/2 R/2
C/2
-model
C
T-model
 3-segment -model is accurate to 3% in simulation
 L-model needs 100 segments for same accuracy!
 Use single segment -model for Elmore delay
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CMOS VLSI Design 4th Ed.
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The Lumped Model
Vout
cwire
Driver
Rdriver
Vout
Vin
Clumped
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CMOS VLSI Design 4th Ed.
Wire RC Delay
 Estimate the delay of a 10x inverter driving a 2x
inverter at the end of the 1 mm wire. Assume wire
capacitance is 0.2 fF/mm and that a unit-sized
inverter has R = 10 KW and C = 0.1 fF.
– tpd = (1000 W)(100 fF) + (1000 + 800 W)(100 + 0.6 fF) = 281 ps
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Wire Energy
 Estimate the energy per unit length to send a bit of
information (one rising and one falling transition) in a
CMOS process.
 E = (0.2 pF/mm)(1.0 V)2
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= 0.2 pJ/bit/mm
= 0.2 mW/Gbps
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Elmore Delay
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Elmore Delay
 0 4   01  1 2   2 3   3 4
 R1 C1  C2  C3  C4  C5  C6 
R2 C2  C3  C4 
1

R3  C3  C4 
2

R4 C4

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The Elmore Delay - RC Chain
53
CMOS VLSI Design 4th Ed.
Wire Model
Assume: Wire modeled by N equal-length segments
For large values of N:
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CMOS VLSI Design 4th Ed.
The Distributed RC Line
 For a distributed line, we have the diffusion equation
V  2V
rc
 2
t x
 This equation has a solution in the s domain
1
Vout s 
scosh sRC

 Vout(t) cannot be solved in closed form.
 It can be approximated by
RC
for t << RC
4t
Vout t   1.0 1.366e 2.5359t RC  0.366e 9.4641t RC
Vout t   2erfc

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CMOS VLSI Design 4th Ed.
for t >> RC
55
Step-response as a function of time and space
2.5
x= L/10
2
voltage (V)
x = L/4
1.5
x = L/2
1
x= L
0.5
0
56
0
0.5
1
1.5
2
2.5
3
time (nsec)
3.5
CMOS VLSI Design 4th Ed.
4
4.5
5
RC Wires – Lumped vs Distributed
Value of Interest
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Lumped RC
Distributed RC
0 -> 50% (tp)
0.69RC
0.38RC
0 -> 63% ()
RC
0.5RC
10% -> 90% (tr)
2.2RC
0.9RC
0 -> 10%
0.1RC
0.1RC
0 -> 90%
2.3RC
RC
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Distributed RC Lines
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CMOS VLSI Design 4th Ed.
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Distributed RC Lines
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CMOS VLSI Design 4th Ed.
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The Transmission Line
l
r
g
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l
r
c
CMOS VLSI Design 4th Ed.
g
c
60
The Transmission Line
 The diffusion equations are
v
i
 ri  l
x
t
i
v
 gv  c
x
t
 2v
v
 2v
 lc 2
2  rc
x
t
t
 First, ignore r. This is a lossless transmission line.

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 2v
 2v
2  lc
x
t 2
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The Transmission Line
 A step input applied to a lossless transmission line
propagates through the line with speed v.
v
1
,
lc
tp 
1
 lc
v
dq
dx
c
i
 c V  cvV 
V
dt
dt
l
Z0 
V
l

I
c
 Z0 is the characteristic impedance and is
independent of length.

 Z0 is between
100W and 500W for typical wires.
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The Transmission Line
 Define a wave reflection coefficient as
r
Vrefl
Vinc
R  Z0

R  Z0
 When a transmission line is being driven by an ideal
source, the termination is important.
– For
a termination of Z0, no reflection.
– For a short circuit termination, r = -1
– For an open circuit termination, r = 1
 See the site http://www.williamsonlabs.com/xmission.htm
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The Transmission Line
 Case 1: Large source resistance and infinite load
resistance. Take RS = 5Z0
 Cycle 1:
 Z 0 
1
Vsource  
Vin  x5V  0.83V
6
Z 0  RS 
– When this wave reaches the destination, it is fully
reflected -> 1.67V.

– It comes back to the source. The source has
become the load.
5Z 0  Z 0 2
rS 
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5Z 0  Z 0
CMOS VLSI Design 4th Ed.

3
64
The Transmission Line
 Case 1 continued
– The new source voltage becomes




2
Vcycle 2  1.67x  1.1
3
We restart the analysis with 1.1 V for cycle 2.
It is obvious that the signal builds up.

However,
the rise time is not determined by any RC
constant. It is in terms of number of reflection cycles
given by length/velocity.
See the site
http://www.eecs.tufts.edu/~alanh/simulation.html
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The Transmission Line
 Case 2: Small source resistance, infinite load
resistance.
– Almost all the signal injected into the transmission
line.
– Reflected from the load. Almost doubles by the
time it comes back to the source.
– The signal is phase reversed at the source as
Z0
 Z0
2
5
rS 

Z0
3

Z
0
5
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The Transmission Line
 Case 2: The signal exhibits severe ringing.
 It takes many cycles before it settles to its final
value.
 Case 3: Matched source resistance.
– Half the signal is injected into the line
– Doubles at the termination.
– Final value is reached within length/velocity.
 Capacitive termination (our case)
– No overshoot, behavior asymptotic to  = Z0CL
– Interesting behavior observed only at source.
14: Wires
CMOS VLSI Design 4th Ed.
67
A Look into the Future
 Ideal Scaling
Parameter Relation
Local
Wire
Constant
Length
Global
Wire
W, H, t
1/S
1/S
1/S
L
1/S
1
1/SC
C
LW/t
1/S
1
1/SC
R
L/WH
S
S2
S2/SC
RC
L2/Ht
1
S2
S2/S2C
 Typically, S = 1.15, SC = 0.94 per year.
– Delay of global wires increases 50% per year.
14: Wires
CMOS VLSI Design 4th Ed.
68
A Look into the Future
 Constant R scaling
Parameter Relation
Local
Wire
Constant
Length
Global
Wire
W,t
1/S
1/S
1/S
H
1
1
1
L
1/S
1
1/SC
C
CLW/t
C/S
C
C/SC
R
LW/H
1
S
S/SC
RC
CL2/Ht
C/S
CS
CS/S2C
 C is introduced to model the extra fringing
capacitance effects.
 As long as C < S, not too bad.
14: Wires
CMOS VLSI Design 4th Ed.
69
Crosstalk
 A capacitor does not like to change its voltage
instantaneously.
 A wire has high capacitance to its neighbor.
– When the neighbor switches from 1-> 0 or 0->1,
the wire tends to switch too.
– Called capacitive coupling or crosstalk.
 Crosstalk effects
– Noise on nonswitching wires
– Increased delay on switching wires
14: Wires
CMOS VLSI Design 4th Ed.
70
Crosstalk Delay
 Assume layers above and below on average are quiet
– Second terminal of capacitor can be ignored
– Model as Cgnd = Ctop + Cbot
 Effective Cadj depends on behavior of neighbors
A
B
– Miller effect
C
Cgnd
B
V
Ceff(A)
MCF
Constant
VDD
Cgnd + Cadj
1
Switching with A
0
Cgnd
0
Switching opposite A
2VDD Cgnd + 2 Cadj 2
14: Wires
CMOS VLSI Design 4th Ed.
adj
Cgnd
71
Crosstalk Noise
 Crosstalk causes noise on nonswitching wires
 If victim is floating:
– model as capacitive voltage divider
Vvictim 
Cadj
Cgnd v  Cadj
Vaggressor
Aggressor
Vaggressor
Cadj
Victim
Cgnd-v
14: Wires
Vvictim
CMOS VLSI Design 4th Ed.
72
Driven Victims
 Usually victim is driven by a gate that fights noise
– Noise depends on relative resistances
– Victim driver is in linear region, agg. in saturation
– If sizes are same, Raggressor = 2-4 x Rvictim
Vvictim 
Cadj
Cgnd v  Cadj
1
Vaggressor
1 k
Raggressor
14: Wires
Cgnd-a
Vaggressor
 aggressor Raggressor  Cgnd a  Cadj 
k

 victim
Rvictim  Cgnd v  Cadj 
CMOS VLSI Design 4th Ed.
Aggressor
Cadj
Rvictim
Victim
Cgnd-v
Vvictim
73
Coupling Waveforms
 Simulated coupling for Cadj = Cvictim
14: Wires
CMOS VLSI Design 4th Ed.
74
Noise Implications
 So what if we have noise?
 If the noise is less than the noise margin, nothing
happens
 Static CMOS logic will eventually settle to correct
output even if disturbed by large noise spikes
– But glitches cause extra delay
– Also cause extra power from false transitions
 Dynamic logic never recovers from glitches
 Memories and other sensitive circuits also can
produce the wrong answer
14: Wires
CMOS VLSI Design 4th Ed.
75
Wire Engineering
 Goal: achieve delay, area, power goals with
acceptable noise
 Degrees of freedom:
– Width
– Spacing
– Layer
– Shielding
0.8
1.8
0.7
Coupling:2Cadj / (2C adj+Cgnd)
2.0
1.6
Delay (ns):RC/2
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.6
0.4
0.3
0.2
0.1
0
0
500
1000
1500
0
2000
1000
500
14: Wires
a1 gnd a2
a3 vdd
vdd a0 gnd a1 vdd a2 gnd
1500
2000
Pitch (nm)
Pitch (nm)
vdd a0
WireSpacing
(nm)
320
480
640
0.5
a0
b0
a1
CMOS VLSI Design 4th Ed.
b1
a2
b2
76
Repeaters
 R and C are proportional to l
 RC delay is proportional to l2
– Unacceptably great for long wires
 Break long wires into N shorter segments
– Drive each one with an inverter or buffer
Wire Length: l
Driver
Receiver
N Segments
Segment
l/N
Driver
14: Wires
l/N
Repeater
l/N
Repeater
Repeater
Receiver
CMOS VLSI Design 4th Ed.
77
Repeater Design
 How many repeaters should we use?
 How large should each one be?
 Equivalent Circuit (Using the PI model)
– Wire length l/N
• Wire Capacitance Cw*l/N, Resistance Rw*l/N
– Inverter width W (nMOS = W, pMOS = 2W)
• Gate Capacitance C’*W, Resistance R/W
14: Wires
CMOS VLSI Design 4th Ed.
78
Repeater Results
 Write equation for Elmore Delay
– Differentiate with respect to W and N
– Set equal to 0, solve
2 RC 
RwCw
l

N
t pd
l
W
14: Wires

 2 2

RCRwCw
~40 ps/mm
in 65 nm process
RCw
RwC
CMOS VLSI Design 4th Ed.
79
Repeater Energy
 Energy / length ≈ 1.87CwVDD2
– 87% premium over unrepeated wires
– The extra power is consumed in the large
repeaters
 If the repeaters are downsized for minimum EDP:
– Energy premium is only 30%
– Delay increases by 14% from min delay
14: Wires
CMOS VLSI Design 4th Ed.
80
Repeaters
 Let us detail the derivation. It is simpler if distributed
analysis is used.
 Using Elmore formulation,


 0.69R
t p  0.69Rdr Cint  CW  C fan  RW (0.38CW  0.69C fan )

 0.69Rdr Cint  C fan

2
c

r
C
L

0.38r
c
L
dr W
W fan
W W
 If there are k identical inverters,


L 2 
L
t p  k 0.69Rdr Cint  C fan  0.69 RdrcW  rW C fan  0.38rW cW   
k  
k


14: Wires



CMOS VLSI Design 4th Ed.

81
Repeaters
 Make some approximations to make problem
simpler.
– Ignore Cint and collect terms

CW
 RW  CW

t p  k 0.7Rdr  C fan 
 0.7C fan 
0.4
 k
 k 

k

 Take the derivative to find the optimum
t p
4RW CW
0k 
k
7RdrC fan
14: Wires
CMOS VLSI Design 4th Ed.
82
Repeaters
 Now, let us try to size the repeaters as well.
 Let us use h to scale them.
 Rdr CW
 RW  CW

t p  k 0.7
 0.7hC fan 
  hC fan 
0.4
 k 

h  k
k

 Now, taking two partial derivatives,
t p
t p
 0,
0
k
h

k
4RW CW
,
7RdrC fan
h
RdrCW
RW C fan
t p,opt  2.5 RdrC fan RW CW
14: Wires
CMOS VLSI Design 4th Ed.
83