Transcript ppt
Introduction to
CMOS VLSI
Design
Lecture 14:
CAMs, ROMs, and PLAs
Credits: David Harris
Harvey Mudd College
(Material taken/adapted from
Harris’ lecture notes)
Outline
Content-Addressable Memories
Read-Only Memories
Programmable Logic Arrays
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 2
CAMs
Extension of ordinary memory (e.g. SRAM)
– Read and write memory as usual
– Also match to see which words contain a key
adr
data/key
read
CAM
match
write
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 3
10T CAM Cell
Add four match transistors to 6T SRAM
– 56 x 43 l unit cell
bit
bit_b
word
cell_b
cell
match
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 4
CAM Cell Operation
address
read/write
14: CAMs, ROMs, and PLAs
CAM cell
clk
CMOS VLSI Design
weak
miss
match0
row decoder
Read and write like ordinary SRAM
For matching:
– Leave wordline low
– Precharge matchlines
– Place key on bitlines
– Matchlines evaluate
Miss line
– Pseudo-nMOS NOR of match lines
– Goes high if no words match
match1
match2
match3
column circuitry
data
Slide 5
Read-Only Memories
Read-Only Memories are nonvolatile
– Retain their contents when power is removed
Mask-programmed ROMs use one transistor per bit
– Presence or absence determines 1 or 0
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 6
ROM Example
4-word x 6-bit ROM
– Represented with dot diagram
– Dots indicate 1’s in ROM
weak
pseudo-nMOS
pullups
A1 A0
Word 0: 010101
Word 1: 011001
Word 2: 100101
Word 3: 101010
2:4
DEC
ROM Array
Y5
Y4
Y3
Y2
Y1
Y0
Looks like 6 4-input pseudo-nMOS NORs
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 7
ROM Array Layout
Unit cell is 12 x 8 l (about 1/10 size of SRAM)
Unit
Cell
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 8
Row Decoders
ROM row decoders must pitch-match with ROM
– Only a single track per word!
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 9
Complete ROM Layout
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 10
PROMs and EPROMs
Programmable ROMs
– Build array with transistors at every site
– Burn out fuses to disable unwanted transistors
Electrically Programmable ROMs
– Use floating gate to turn off unwanted transistors
– EPROM, EEPROM, Flash
Source
Gate
Drain
Polysilicon
Floating Gate
Thin Gate Oxide
(SiO2)
n+
n+
p
14: CAMs, ROMs, and PLAs
bulk Si
CMOS VLSI Design
Slide 11
Building Logic with ROMs
Use ROM as lookup table containing truth table
– n inputs, k outputs requires __ words x __ bits
– Changing function is easy – reprogram ROM
Finite State Machine
– n inputs, k outputs, s bits of state
– Build with ________ bit ROM and ____ bit reg
inputs
n
ROM Array
2n wordlines
DEC
inputs
n ROM k
s
outputs
k
s
state
k outputs
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 12
Building Logic with ROMs
Use ROM as lookup table containing truth table
– n inputs, k outputs requires 2n words x k bits
– Changing function is easy – reprogram ROM
Finite State Machine
– n inputs, k outputs, s bits of state
– Build with 2n+s x (k+s) bit ROM and (k+s) bit reg
inputs
n
ROM Array
2n wordlines
DEC
inputs
n ROM k
s
outputs
k
s
state
k outputs
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 13
Example: RoboAnt
Let’s build an Ant
Sensors: Antennae
(L,R) – 1 when in contact
Actuators: Legs
Forward step F
Ten degree turns TL, TR
Goal:
L
R
make our ant smart enough to
get out of a maze
Strategy: keep right antenna on wall
(RoboAnt adapted from MIT 6.004 2002 OpenCourseWare by Ward and Terman)
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 14
Lost in space
Action: go forward until we hit something
– Initial state
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 15
Bonk!!!
Action: turn left (rotate counterclockwise)
– Until we don’t touch anymore
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 16
A little to the right
Action: step forward and turn right a little
– Looking for wall
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 17
Then a little to the right
Action: step and turn left a little, until not touching
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 18
Whoops – a corner!
Action: step and turn right until hitting next wall
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 19
Simplification
Merge equivalent states where possible
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 20
State Transition Table
Lost
RCCW
Wall1
Wall2
S1:0
00
00
00
01
01
01
10
10
11
11
11
L
0
1
0
1
0
0
X
X
1
0
0
14: CAMs, ROMs, and PLAs
R
0
X
1
X
1
0
0
1
X
0
1
S1:0’
00
01
01
01
01
10
10
11
01
10
11
TR
0
0
0
0
0
0
1
1
0
0
0
CMOS VLSI Design
TL
0
0
0
1
1
1
0
0
1
1
1
F
1
1
1
0
0
0
1
1
1
1
1
Slide 21
ROM Implementation
16-word x 5 bit ROM
L, R
S1 S0 L R
TL, TR, F
ROM
S'1:0
S1:0
0000
0001
0010
0011
0100
4:16 DEC
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
S1' S0' TR'TL' F'
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 22
ROM Implementation
16-word x 5 bit ROM
L, R
S1 S0 L R
TL, TR, F
ROM
S'1:0
S1:0
0000
0001
0010
0011
0100
4:16 DEC
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
S1' S0' TR'TL' F'
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 23
PLAs
A Programmable Logic Array performs any function
in sum-of-products form.
Literals: inputs & complements
Products / Minterms: AND of literals
Outputs: OR of Minterms
bc
AND Plane
OR Plane
Example: Full Adder
s abc abc abc abc
cout ab bc ac
a
b
Inputs
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
c
s
Minterms
ac
ab
abc
abc
abc
abc
cout
Outputs
Slide 24
NOR-NOR PLAs
ANDs and ORs are not very efficient in CMOS
Dynamic or Pseudo-nMOS NORs are very efficient
Use DeMorgan’s Law to convert to all NORs
AND Plane
a
b
OR Plane
AND Plane
bc
bc
ac
ac
ab
ab
abc
abc
abc
abc
abc
abc
abc
abc
c
a
s
14: CAMs, ROMs, and PLAs
OR Plane
b
c
s
cout
CMOS VLSI Design
cout
Slide 25
PLA Schematic & Layout
AND Plane
OR Plane
bc
ac
ab
abc
abc
abc
abc
a
b
c
s
14: CAMs, ROMs, and PLAs
cout
CMOS VLSI Design
Slide 26
PLAs vs. ROMs
The OR plane of the PLA is like the ROM array
The AND plane of the PLA is like the ROM decoder
PLAs are more flexible than ROMs
– No need to have 2n rows for n inputs
– Only generate the minterms that are needed
– Take advantage of logic simplification
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
Slide 27
Example: RoboAnt PLA
Convert state transition table to logic equations
S1:0
00
00
00
01
01
01
10
10
11
11
11
L
0
1
0
1
0
0
X
X
1
0
0
R
0
X
1
X
1
0
0
1
X
0
1
S1:0’
00
01
01
01
01
10
10
11
01
10
11
14: CAMs, ROMs, and PLAs
TR
0
0
0
0
0
0
1
1
0
0
0
TL
0
0
0
1
1
1
0
0
1
1
1
F
1
1
1
0
0
0
1
1
1
1
1
CMOS VLSI Design
TR S1 S0
TL S0
F S1 S0
Slide 28
RoboAnt Dot Diagram
AND Plane
OR Plane
S1' S1 S0 LS1 LRS0
S0
S1
S0
LS 0
S 0' R LS1 LS0
TR S1 S0
TL S0
LS1
R
LRS 0
LS1
S1 S 0
F S1 S0
S1
S0
L
R
S1 ' S0 ' TR
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
TL F
Slide 29
RoboAnt Dot Diagram
AND Plane
OR Plane
S1' S1 S0 LS1 LRS0
S0
S1
S0
LS 0
S 0' R LS1 LS0
TR S1 S0
TL S0
LS1
R
LRS 0
LS1
S1 S 0
F S1 S0
S1
S0
L
R
S1 ' S0 ' TR
14: CAMs, ROMs, and PLAs
CMOS VLSI Design
TL F
Slide 30